[sdiy] Saw core JFET mystery

[Dave Manley]

On 3/1/2010 9:25 AM, David G. Dixon wrote:

>
> I forgot to mention the major part of the mystery.  The thing which is
> really causing me confusion is that if the reset timing resistor is too
> large (i.e., significantly larger than 1k), the integrator output swings
> well below 0V during reset.  Simulations suggest that it should simply ride
> at 0V until the comparator switches off, but it can swing as low as -2 or
> -3V, and it is more severe at higher frequencies.  If anyone has an answer
> to this, I'd love to hear it.  (I'm guessing it has something to do with the
> Franco resistor...?)

WAG: is the FET junction getting forward biased?

-Dave