[sdiy] Saw core JFET mystery

[Eric Brombaugh]

A Franco Resistor was a political dissident opposed to regime of Spanish 
fascist dictator Francisco Franco during his rule from 1939-1978. Many 
of these people were tortured and/or put to death, hence the common 
phrase "It is useless to be a resistor", or sometimes "Resistance is 
futile".

Perhaps David meant the "De Franco resistor", a technique discovered by 
Sergio De Franco to improve the response time of JFET reset transistors 
in VCOs? Googling turns up these documents with some details:

http://www.oakleysound.com/vco4-doc.pdf
http://www.oakleysound.com/vco5-bg.pdf

Eric

On 03/01/2010 12:53 PM, cheater cheater wrote:
> David,
> could you please tell me what a Franco resistor is?
>
> Do you have a schematic up so that we can talk about this more precisely?
>
> Thanks
> D.
>
> 2010/3/1 David G. Dixon<dixon at interchange.ubc.ca>:
>>> What is your voltage discharge swing?
>>
>> 5V ramp, 1nF cap, PN4391 JFET (rated at 30 ohms on-resistance).  The
>> discharge time should be on the order of 150 to 200ns, if I'm not mistaken).
>>
>> The reset circuit is simplicity itself: JFET gate wired directly to
>> comparator output, 680-ohm Franco resistor (based on simulations, which are
>> obviously crap), 1k timing resistor, 22pF timing cap, 2.2k comparator
>> pullup.  That's it.
>>
>> I forgot to mention the major part of the mystery.  The thing which is
>> really causing me confusion is that if the reset timing resistor is too
>> large (i.e., significantly larger than 1k), the integrator output swings
>> well below 0V during reset.  Simulations suggest that it should simply ride
>> at 0V until the comparator switches off, but it can swing as low as -2 or
>> -3V, and it is more severe at higher frequencies.  If anyone has an answer
>> to this, I'd love to hear it.  (I'm guessing it has something to do with the
>> Franco resistor...?)
>>
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