[sdiy] Inverting Amplifier as a Buffer Output.

Oscar Salas osaiber at yahoo.es
Wed Jun 23 23:38:33 CEST 2010


Thanks all for your replies.

I forgot to say that my question about these buffer outputs are within the context of a modular synthesizer. So we can expect 100K input impedances and 1K output impedance (A) or near 0 output impedance (B)

A question please scroll down:
--- On Wed, 6/23/10, Speth, John <John.Speth at coherent.com> wrote:

> From: Speth, John <John.Speth at coherent.com>
> Subject: Re: [sdiy] Inverting Amplifier as a Buffer Output.
> To: "synth-diy at dropmix.xs4all.nl" <synth-diy at dropmix.xs4all.nl>
> Date: Wednesday, June 23, 2010, 1:04 AM
> For both cases, the right-most
> resistor limits the current that the op-amp will supply when
> the next stage input resistance is low.  Since case B's
> resistor is in the feedback loop, the voltage at the next
> stage input will track with the input with whatever scaling
> the other resistors provide.  The downside is that it
> could drive the op-amp output out of compliance if the next
> stage input resistance is too low.  There is no such
> regulation with case A.
> 
> That's the tradeoff.  It's up to you to assign value
> in terms of "advantage" or "disadvantage" based on your
> application.
> 
> John Speth
> mailto:john.speth at coherent.com

In which way could the case B) drive the opamp out of compliance if there is low input impedance. What I should expect?



> > -----Original Message-----
> > From: synth-diy-bounces at dropmix.xs4all.nl
> [mailto:synth-diy-
> > bounces at dropmix.xs4all.nl]
> On Behalf Of Oscar Salas
> > Sent: Tuesday, June 22, 2010 2:11 PM
> > To: synth-diy at dropmix.xs4all.nl
> > Subject: [sdiy] Inverting Amplifier as a Buffer
> Output.
> >
> >
> > Hello all,
> >
> > I have drawn below two different configurations of an
> inverting
> > amplifier as buffer output:
> > A) The feedback resistor is taped -before- the output
> resistor.
> > B) The feedback resistor is taped -after- the output
> resistor.
> >
> > The case A) has voltage drop when it is conected to
> another module
> > input.
> > This is solved in the case B) where there is not
> voltage drop.
> > So, it seems a better solution.
> >
> > What advantages has the case A) versus the case B) if
> any?
> >
> >
> >               
>              
> ----/\/\/\/\-------
> >               
>               | 
>            
>    |
> > A)             
>              | 
>            
>    |
> >               
>               | 
> =              |
> >               
>               | 
> =   =          |
> >   
>    -----------/\/\/\/\-------= 
> --   =      |
> >               
>              
>    =       
>    =-----------/\/\/\/\
> >               
>          
>    ----=  +    =
> >               
>             |   
> =   =
> >               
>             |    =
> >               
>           __|__
> >
> >
> >
> >               
>              
> ----/\/\/\/\----------------
> >               
>               | 
>                
>          |
> > B)             
>              | 
>                
>          |
> >               
>               | 
> =               
>         |
> >               
>               | 
> =   =         
>           |
> >   
>    -----------/\/\/\/\-------= 
> --   =         
>       |
> >               
>              
>    =       
>    =---/\/\/\/\----------
> >               
>          
>    ----=  +    =
> >               
>             |   
> =   =
> >               
>             |    =
> >               
>           __|__
> >
> >
> >
> >
> > _______________________________________________
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