[sdiy] Does Source = Drain???

[ASSI]

On Sunday 13 June 2010, John Richetta wrote:
> Like David Ingebretsen, I've had similar questions recently, and
> have gone looking for answers.

Some literature concerning JFET that may or may not have turned up in 
your search:

Motorola AN211A: Field Effect Transistors in Theory and Practice
Siliconix AN105: FET as Voltage-Controlled Resistors
National AN-32: FET Circuit Applications

> Most books I have don't even state that drain
> and source are interchangeable; the few that do don't say much
> about the cases where this might not be true.  Apparently, there
> are JFETs with "optimized geometry" that will function OK
> "backward" but not as well - no mention of exactly what the
> consequences might be.

The simplest of the JFET is symmetrical and if there's no really good 
reason to change that (like in an RF JFET where you want to minimize 
some capacitances at the expense of others) everybody just leaves it 
that way.

> In my self-education about JFETs, I came across another point that
> I hope the SDIY list can shed light on: what exactly happens when
> the gate voltage goes positive, relative to drain (or source!) in
> an N- channel FET?  Most documents simply state the that gate is
> then "forward biased" (no kidding) and that "this is not often
> done."

Well, a JFET gate is simply a pn-junction.  Forward biased means just 
that, it starts to conduct and the current that flows will end up in 
the source (source = the terminal with the lowest potential).

> Well, OK.  Fine.  But how about providing some useful
> characterization of transistor behavior?  In fact, some datasheets
> do seem to provide this.  And, while it should be clear that gate
> impedance is *many* orders of magnitude decreased in such a mode
> of operation, it also seems clear to me, based on typical curves,
> that this can in fact be a useful way to operate JFETs - it
> extends their range of conductance and control, potentially
> beneficially in some applications.  It appears that one must be
> careful to limit gate current, of course.

It doesn't really extend the _range_ of control since there is almost 
no junction width modulation when the diode becomes forward biased 
(that is what controls the channel width and hence the resistance in a 
JFET).  If you limit the gate current, then of course the forward bias 
is also limited.  Positive gate voltages up to about 0.4-0.6V can be 
useful, but that's about it.  This mode of operation has been used for 
ages and I've seen a good number of pre-amplifier circuits that use a 
JFET with a small signal centered at 0V at their gate (this saves the 
bias network and the associated noise).


Achim.
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