[sdiy] Does Source = Drain???

[Antti Huovilainen]

On Sun, 13 Jun 2010, John Richetta wrote:

> In my self-education about JFETs, I came across another point that I 
> hope the SDIY list can shed light on: what exactly happens when the gate 
> voltage goes positive, relative to drain (or source!) in an N-channel 
> FET?  Most documents simply state the that gate is then "forward biased" 
> (no kidding) and that "this is not often done."  Well, OK.  Fine.  But 
> how about providing some useful characterization of transistor behavior?

There's a parasitic diode from the gate to the acting drain (the non-gate 
terminal with the highest voltage).

If you have a scope (preferably digital), you can actually characterize 
this and the source/drain equivalence for low frequency signals yourself. 
As long as you limit the maximum current to sane value (say, < 1 mA), the 
jfet will not be damaged by reverse operation AFAIK.

Antti

"No boom today. Boom tomorrow. There's always a boom tomorrow"
   -- Lt. Cmdr. Ivanova