[sdiy] Does Source = Drain???

[John Richetta]

> On Jun 13, 2010, at 1:20 AM, David Ingebretsen wrote:
>> I was building the VCO core for my Steiner project and I  
>> inadvertently
>> swapped the drain and source on the JFET. The circuit still worked. I
>> re-read about JFETS, but didn't find a satisfactory answer. Can the  
>> Drain
>> and Source be swapped in any circuit? That is, are they essentially  
>> the
>> same
>> electrically?
>>
>> I bought a Peak, Atlas DCA semiconductor analyzer, and it can't
>> distinguish
>> from the source and drain either.

On Jun 13, 2010, at 2:00 AM, David G. Dixon wrote:
> Every datasheet I've ever read on JFETs always says that the source  
> and
> drain are interchangeable, right on the front page.  I don't think it
> matters.  I'd say, orient them for maximum layout convenience.

Like David Ingebretsen, I've had similar questions recently, and have  
gone looking for answers.  I am basically a rank amateur, and back  
when I was last dabbling with electronics, as a teenager in the mid- 
eighties, FETs were not a really well understood part of popular, low- 
end electronics know-how.  So, I recently decided to try and formalize  
my understanding of all types of transistors, and was surprised to  
learn of some not-so-well understood things, such as the existence of  
many kinds of "FET"; the interchangeable drain-source of many, but not  
all, JFETs; and of FETs with multiple drains / sources / gates, etc.

I surely have not looked at every JFET datasheet, but I have looked at  
a couple dozen or so, and I think I've found exactly one that  
straightforwardly claims drain and source are interchangeable.  A  
while back, I wrote an e-mail to this list (but never sent it) that  
asked if there was a not-sufficiently-obvious-to-me way to deduce this  
from transistor property graphs, precisely because so few datasheets  
seem to state this.  In fact, I've found that discussion of JFETs is  
surprisingly spotty, regarding some important points, in both  
conventional transistor texts, and many on-line articles.  Most books  
I have don't even state that drain and source are interchangeable; the  
few that do don't say much about the cases where this might not be  
true.  Apparently, there are JFETs with "optimized geometry" that will  
function OK "backward" but not as well - no mention of exactly what  
the consequences might be.

I find it startling that such a useful property of JFETs is so little  
recognized, at least in amateur texts.  I've been dabbling with an  
idea I've had for a seemingly relatively simple four-quadrant  
multiplier, built from JFETs used as voltage controller resistors   
(VCRs), with some op-amp assistance.  In this circuit, along with many  
others that might use JFET VCRs, it strikes me that the nonpolarized  
nature of the drain-to-source channel is a vital characteristic.   
Certainly, in "my" four-quadrant multiplier design, it's critical.   
Many sources suggest that JFETs have limited utility, but this  
characteristic alone makes them hugely valuable to me - in contrast to  
discrete "MOS" FETs and "IG" FETs, essentially all of which (as I  
understand it) have the perhaps necessary but nonetheless annoying  
protection diode - which completely precludes application as a  
bidirectional resistance.

In my self-education about JFETs, I came across another point that I  
hope the SDIY list can shed light on: what exactly happens when the  
gate voltage goes positive, relative to drain (or source!) in an N- 
channel FET?  Most documents simply state the that gate is then  
"forward biased" (no kidding) and that "this is not often done."   
Well, OK.  Fine.  But how about providing some useful characterization  
of transistor behavior?  In fact, some datasheets do seem to provide  
this.  And, while it should be clear that gate impedance is *many*  
orders of magnitude decreased in such a mode of operation, it also  
seems clear to me, based on typical curves, that this can in fact be a  
useful way to operate JFETs - it extends their range of conductance  
and control, potentially beneficially in some applications.  It  
appears that one must be careful to limit gate current, of course.

Am I badly confused, or at least partly right?  Can someone explain  
whether this mode of operation might be useful, or why it should  
always be avoided?  Anyone want to recommend a truly up-to-date and  
complete transistor reference, that is still useful in the context of  
hobbyists dealing with discrete (as well as IC) transistors (as  
opposed to a reference intended just for those designing integrated  
circuits)?  Such texts seem to be almost impossible to find (thus,  
lots of time spent on my part reading a variety of sources, piecing  
little bits together, in a fairly non-authoritative fashion).

Thanks in advance for any JFET edification!  -jar

P.S. - If someone feels that this question is too amateurish or  
ignorant, please say so politely.  I'll get the message - thanks!