[sdiy] SRAM question

[Colin f]

> Sometimes there is additional protection circuitry to prevent 
> the processor from accidentally writing to RAM during power 
> up/down when it might do unpredictable things.

There should always be protection circuitry.
You need to detect power-down as soon as it happens and deselect the RAM
chip before any spurious writes can occur.
This can often be done by the circuitry that holds the CPU in reset when the
supply voltage is too low. 
Deselecting a low power SRAM chip will usually put it into its standby power
mode, with all outputs in high-impedance state.
Remember you need to keep the device deselected once power in the rest of
the circuit is down.
So if the RAM chip only has active low chip enable lines, these are going to
need pulled high by the battery voltage when the rest of the circuit is off.
6264 SRAMs used to have an active high chip select line that made life
easier...
 
> While this was pretty common 10-20 years ago, these days more 
> often you'll find long-term storage is done with flash memory 
> or EEPROM which needs no battery to retain its data.

The problem with flash or EPROM is the endurance of data.
If you have frequently changing data in memory that you want to be
non-volatile without having to initiate an explicit store operation before
power-down, then battery backed SRAM is the answer.
One possible alternative to save the cost of the battery and power
switchover circuitry is FRAM.
But don't believe their hype about it being a drop-in replacement for SRAM -
it needs the CE line toggled to latch every new address in.

Cheers,
Colin f