[sdiy] self-modifying code was: Re: My latest project

[cheater cheater]

Let's not go overboard - certainly, you can start out with dynamic
swapping of images, just the way people do that in ASM. I don't see
people doing dynamic recompilation that much in C. To do JIT/dynamic
recompilation you usually need a different type of architecture,
whether it's software, hardware, or fpga which is halfway between
them... er, uh, shartware. :P

This dynamic reconfiguration is interesting. Maybe you can tell us
something more about this? What are you doing with it?
I think it might be good for long functions that are made out of very
very small blocks that would otherwise require a lot of  transfering
of data, switching context, etc... Just set up a pipeline and have the
function execute in 1 cycle afterwards. Could be good for shaders and
other stuff like that I guess. Is this one of the applications you are
looking at for your architecture? I guess generally SIMD would be nice
to do with this, and other than that just being able to use
complicated functions a lot and have them be quick is a nice
situation.

I could easily imagine a special interface for 'building blocks' that
could allow them to be placed next to each other easily to turn them
into pipelines.. sort of like lego. This might even take up a lot of
space, but it could easily lead to a situation where the problem is
easy to solve, and just needs optimization. It could be similar to
what assembler is in software.

D.

On Thu, Feb 18, 2010 at 19:45, Rainer Buchty <rainer at buchty.net> wrote:
> On Thu, 18 Feb 2010, cheater cheater wrote:
>
>> "because auf zhe place und raute effort I dont knov whezzer".. ;-)
>
> There you see how speaking two languages messes up the language processor.
>
> Btw, you wouldn't use "auf" here in German, but pronounced English it
> matches the sound of "of". So much for that ;)
>
>> Seriously though: the FPGA is great because you can reconfigure it
>> when you need.. It would be nice to be able to have that need more
>> often than once per boot. You could even think of a reduced
>> instruction set CPU which sets up pipelines for additional
>> instructions as and when they are needed - substantially removing the
>> die size needed, while still giving you the whole range of
>> capabilities..
>
> Welcome to part of my research -- Self-X architectures ;)
>
> But dynamical P&R is out of the question, you certainly don't want to do
> that with average FPGAs.
>
> Some time ago there was a research project (cf. Warp Processor) which used a
> dedicated architecture (2 ARM cores and a restricted FPGA logic) for dynamic
> architecture alteration (loop support, block synthesis). Here, the FPGA was
> quite stripped down so that a (40MHz IIRC) ARM core is able to perform P&R
> within a matter of seconds.
>
> Rainer
>
>