[sdiy] LTSpice problem

[Stewart Pye]

Yes, that makes sense. I'll just have to figure out how to delay the 
graphing of data in LTspice...

Regards,
Stew.


Harry Bissell wrote:
> How long was your simulation run ? It ~is~ real life in the short term if you
> assume the capacitor started at 0V.
>
> I'm not an LT Spice guru, but I think you can specify when it starts taking
> data to graph. Wait an appropriate time, then start graphing. With 10uF and
> 100K, I'd expect it to take about 5 seconds to get centered around zero volts
>
> (100K * 10uF) * 5   (5RC)
>
> You might be able to specify the start voltage as something other than zero, you
> could calculate where you expected the cap to be, and start with that value.
>
> H^) harry
>
>
>
> ----- Original Message -----
> From: Stewart Pye <stewpye at optusnet.com.au>
> To: Synth DIY <synth-diy at dropmix.xs4all.nl>
> Sent: Wed, 01 Dec 2010 14:52:13 -0500 (EST)
> Subject: [sdiy] LTSpice problem
>
> Hi,
>
> In LT Spice I have the output of a transistor diff amp going into a 10uF 
> capacitor then a 100k resistor to ground. At the junction of the 10uF 
> cap and the 100k resistor I would expect to see the waveform (almost 
> symmetrical sine wave) to centre around 0V, however it goes from -0.04V 
> to 5.2V. Has anyone seen this behaviour in LTSpice or know if this would 
> be a real world problem. I've always assumed that if you capacitively 
> couple the signal and provide a dc path to ground then the signal will 
> centre around 0V...
>
> Cheers,
> Stew.
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