[sdiy] LTSpice problem

Stewart Pye stewpye at optusnet.com.au
Wed Dec 1 20:52:13 CET 2010


Hi,

In LT Spice I have the output of a transistor diff amp going into a 10uF 
capacitor then a 100k resistor to ground. At the junction of the 10uF 
cap and the 100k resistor I would expect to see the waveform (almost 
symmetrical sine wave) to centre around 0V, however it goes from -0.04V 
to 5.2V. Has anyone seen this behaviour in LTSpice or know if this would 
be a real world problem. I've always assumed that if you capacitively 
couple the signal and provide a dc path to ground then the signal will 
centre around 0V...

Cheers,
Stew.



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