[sdiy] Digital filtering question

[Antti Huovilainen]

On Tue, 24 Aug 2010, Wooster Audio wrote:

>> You're probably better off using cascaded 1st order sections with global 
>> feedback. Then 18 bits is plenty enough for the multiplies and double 
>> precision accumulators are cheap in FPGA.
> Thats what I am doing, sorry I spoke imprecisely.  I am using the 
> "compromise" filter from Stilson's paper.  I'd like to switch to try your 
> filter, but I don't quite understand how to implement it yet.  I'm still 
> playing around with different tanh implementations and Vt values.

Forget Vt and simply use an arbitrary scaling factor for the tanh (call it 
'drive' in the UI). That's how the analog versions work too - the voltage 
divider at filter input is set more or less by ear so that self 
oscillation amplitude is "balanced" with the input signal.

As for the filter structure, compromise version with the tanh 
nonlinearities embedded works well. Each RC section can be implemented as

(A = 1/1.3, B = 0.3/1.3)

t1 = tanh(x);
y = y + g*(t1*A + t2*B - ty);
t2 = t1;
ty = tanh(y);

For the linear filter, you simple remove the tanh() evaluations. This way 
the multiplier resolution mainly affects cutoff resolution while having 
little effect to SNR. IIRC, this is equivalent to 1st order noise shaping.

Cutoff resolution can be further improved (probably unnecessary) by 
observing that for low cutoffs, g is close to zero. The multiplier output 
can be shifted right and g shifted left by equal amount. I think E-Mu used 
this trick to fit 32 multipole filters in a single ASIC back in the early 
90s (low resolution multiplier combined with barrel shifter).

Antti

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