[sdiy] Digital filtering question

[ASSI]

On Tuesday 24 August 2010, Wooster Audio wrote:
> One area where you really need the extra bits in an IIR filter is an
> ADSR.  I tried to approximate an exponential curve using an 18-bit IIR,
> and could not get a good range of envelope times.  At some point x(n)
> effectively equals x(n-1) and it stops moving.  I think I calculated I
> would need 26 bits.  I switched to an NCO-based ADSR with exponential
> look-up table shaper and am much happier.

It's all linear until it sinks into the truncation noise, so you can scale 
at any time by any factor - lets say 2^n - and still get the same response.  
If you appropriately shift the input and output bits of the filter core 
(that's why you chose a power of two for the factors) and maybe add some 
dither, the only thing that needs more bits is the state (for keeping track 
of the "exponent").  Yes, that's a kind-of-FP implementation, but it doesn't 
cost much in an FPGA.  Much less than adding an extension to the multiplier, 
anyway.  As Antti said, usually the accumulator is first to need more bits 
even when you stick to fixed point, but probably not all 36 that the 
multiplier potentially provides (that helps to keep the speed up).


Achim.
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