[sdiy] BLIT/BLEP virtual analogue synthesis

[Wooster Audio]

What sample bit depth are people using on their FPGA synth audio path?  
I've been going with 18 (the multiplier size) because I haven't been 
able to synthesize larger multipliers due to congestion.

On 8/4/2010 11:54 AM, Antti Huovilainen wrote:
> Combining all this, you could probably get by with 32/16 bit division. 
> After rollover, the phase accumulator is never higher than the phase 
> increment, and thus the division result is less than phase increment. 
> This allows using relatively simple pseudo-floating point to improve 
> the accuracy. 

Has anybody implemented a 32/16 divider like Antti mentions on a FPGA?

Nathan