[sdiy] BLIT/BLEP virtual analogue synthesis

[Scott Gravenhorst]

Olivier Gillet <ol.gillet at gmail.com> wrote:
>> I've designed a system with 192 oscillators @48KHz each with 4 different
>> waveforms (random, square, triangle and pseudo-sin), a 32-bit phase
>> accumulator, 4 phase values per waveform segment (quad-phase distortion), a
>> 4-coefficient FIR filter (7 multipliers) and stereo output as a "block".
>
>Interesting... which method was used for band-limiting?
>
>I'm trying to ponder the balance between brute-forcing or using many
>clock cycles per oscillator to do the band-limited synthesis. I have a
>feeling that BLEP, with its variable length lists of compensation
>terms to sum, does not translate that well into a hardware pipeline.
>
>> On a Spartan 3E-500, I could have 4 blocks on the FPGA, so 768 oscillators.
>> I could reduce the number of oscillators to increase the frequency though -
>> it was purely a for loop for each oscillator. The slowest bit was the FIR
>> filter, which, from memory, was about 12 clock cycles per oscillator. The
>> phase accumulator was 4 clock cycles
>
>To all: which entry-level FPGA dev boards do you recommend - knowing
>that I'd rather use a development environment that works on OS X or
>Linux? Any good book/resource to get started on VHDL/verilog?

http://www.em.avnet.com/evk/home/0,1707,RID%253D0%2526CID%253D46501%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526LID%253D32232%2526PRT%253D0%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html

This board has a 400K gate Spartan-3A (20 mult/20 BRAM) part on it.  No DAC on board.

With this board, I've done several 8 voice polysynths and an 8 operator (fixed algorithm)
16 voice FM polysynth.

This one is, IMO, particularly inexpensive for what it does.



I learned Verilog mostly from here:

http://www.asic-world.com/verilog/veritut.html



-- ScottG
________________________________________________________________________
-- Scott Gravenhorst
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