[sdiy] BLIT/BLEP virtual analogue synthesis

[Olivier Gillet]

> throughput.  You'll likely run out of ideas before you run out of hardware
> and there are _much_ larger FPGA out there.  :-)  If you really fancy the
> absurdly-high sampling rate concept, there are Xilinx eval boards that come
> with a dual channel 125MHz DAC (12bit IIRC).

If I wanted absurdly high sampling rates, I would directly do analog.
Not sure at which clock rate mother nature (or the Matrix) runs but
I'm sure it beats 125 MHz.

Now I understand the flaw in my "brute-force -> sigma-delta" idea. In
a typical use scenario, the oversampled signal that enters the
sigma-delta loop doesn't contain any frequencies above the nyquist
frequency of the input signal (say 24kHz for a 48kHz). But what
happens when sending into a sigma-delta loop a signal with frequencies
filling up the full band (as in the "brute force oversampling
oscillator" case)? Is there some kind of aliasing taking place? Or is
it "just" that the output signal will contain a lot of high-frequency
junk that will need to be filtered?

Olivier