[sdiy] BLIT/BLEP virtual analogue synthesis

[ASSI]

On Wednesday 04 August 2010, Olivier Gillet wrote:
> Eric, you seem to have already played with this: how many FF / LUT4 /
> cells or whatever is used to measure FPGA capacity are taken by a
> "brute-force" triangle / PWM / saw oscillator with a 32 bits phase
> counter, a 24 bits phase increment register, an 8 bits PW register,
> and a 2 bits waveform register?

A phase accumulator in Spartan3A-400 takes about 1% of the available 
resources and could be run at more than 140MHz wihtout trying too hard.  My 
somewhat naive DPW implementation takes one of the precious 20 multipliers 
for squaring and another percent resources for the subtractor and runs at 
roughly the same speed if the multiplier gets properly pipelined.  Amplitude 
scaling will need another multiplier rather than the shifter I currently 
use, or else you'll time-share the multiplier you already have for half the 
throughput.  You'll likely run out of ideas before you run out of hardware 
and there are _much_ larger FPGA out there.  :-)  If you really fancy the 
absurdly-high sampling rate concept, there are Xilinx eval boards that come 
with a dual channel 125MHz DAC (12bit IIRC).


Achim.
-- 
+<[Q+ Matrix-12 WAVE#46+305 Neuron microQkb Andromeda XTk Blofeld]>+

SD adaptations for KORG EX-800 and Poly-800MkII V0.9:
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