[sdiy] BLIT/BLEP virtual analogue synthesis

[Eric Brombaugh]

On 08/04/2010 01:15 PM, Olivier Gillet wrote:
> Eric, you seem to have already played with this: how many FF / LUT4 /
> cells or whatever is used to measure FPGA capacity are taken by a
> "brute-force" triangle / PWM / saw oscillator with a 32 bits phase
> counter, a 24 bits phase increment register, an 8 bits PW register,
> and a 2 bits waveform register?

Not a lot - one of the designs that I have provides 16 oscillators with 
various waveshapes, LFOs, etc and takes up ~900 flipflops/1200 LUTs. 
That's about 40% of a low-end Xilinx Spartan 3e 250K FPGA. Could 
probably squeeze it into the cheaper $6 50k Spartan 3A part if you were 
willing to leave out some features...

Eric