[sdiy] BLIT/BLEP virtual analogue synthesis

[Olivier Gillet]

> Yes, but there's got to be a DAC on the end of the signal chain and the one
> I'm using clocks at 192kHz currently.

I thought about that too, but what I had in mind was a setup without
DAC or the kind of 1-bit / Mhz clocked DAC parts developed eg for
SACD.

> Too much oversampling doesn't really
> buy you much, but needs lots of resources.  If you only want a single
> oscillator or two, brute-forcing high sample rates is probably even a good
> option, but I'm looking to have many oscillators and I don't even want to be
> completely alias-free.

I thought FPGAs would be quite good at this kind of brute forcing. But
I've never written a line of verilog...

Eric, you seem to have already played with this: how many FF / LUT4 /
cells or whatever is used to measure FPGA capacity are taken by a
"brute-force" triangle / PWM / saw oscillator with a 32 bits phase
counter, a 24 bits phase increment register, an 8 bits PW register,
and a 2 bits waveform register?