[sdiy] BLIT/BLEP virtual analogue synthesis

[Eric Brombaugh]

On 08/04/2010 11:49 AM, Olivier Gillet wrote:
> I'm curious about the FPGA bit, and can't help asking a very naive
> question. If a FPGA was to be used for waveform generation, wouldn't
> it make more sense to use it to render at a 10 MHz or 20 Mhz clock
> rate the very naive things (phase_<  0x800000 ? -32768 : 32767 for
> square, etc...) like older sound chips did?

Depends on what you're trying to do in the FPGA. If you're interested in 
generating massive numbers of oscillators via resource sharing as Jim 
Patchell was doing (512 oscillators at once) then you don't have the 
option to run them all at 10 or 20 MHz without spending a lot on your 
FPGA. For systems like this a simple anti-aliasing approach would be 
highly desirable.

On the other hand, if your goals are to have just a few oscillators then 
it's fairly trivial to run them at a very high sample rate and use 
bandlimited decimation to get them down to rates that a common audio DAC 
can accomodate. I've got some prototype designs that generate a small 
number of simple sawtooths at around 1MHz, sum them together and 
downsample to 48kHz which sound quite good. Rough estimate at these 
rates suggest that for a 1kHz saw the in-band aliases will be about 60dB 
down - not too bad in comparison to the spectra in Antti's IEEE paper.

Eric