[sdiy] BLIT/BLEP virtual analogue synthesis

[cheater cheater]

On Wed, Aug 4, 2010 at 16:18, Olivier Gillet <ol.gillet at gmail.com> wrote:
>> However, for the BLEP, I need to know the sub-sample position of the ramp discontinuity. If the sub-sample position is designated "a", then the accumulator value after a wraparound is (1-a) * increment. I can detect the wraparound and divide the accumulator value by the increment to find the sub-sample position, but this is a division by (probably) a 32-bit number.
>>
>> Is there a way to do it that avoids the big ugly division?
>
> I assume you're working on an architecture where divisions are done in
> software. I haven't thought much about it but I think you could use
> prior knowledge about the number of bits in the result to unroll the
> loop of the binary division algorithm. You know that the result will
> be between 0 and 1, the compiler does not.
>
> Let's say you use a 16 bits phase counter positioned at 64000, with a
> phase increment of 2400. The phase parameter of the blep will depend
> on ((6400 + 2400) % 65536) / 2400 = 1536 / 2400. That's the division
> you're talking about, right?

actually it seems the numbers should be: (64000 + 2400) mod 65536 = 864
just a nitpick!

you've explained this 'between zero and 1' and 'only last few bits
used' thing much better than I could even begin to :)

> You won't use the number 1536/2400 anyway since you're working with
> integers... You'll probably want to compute something which is more
> like 256 * 1536 / 2400. So the division you really have to do is
> 393216 / 2400. Now there's a bit of knowledge you know and the
> standard software implementation of / generated by your compiler
> doesn't know: the result will always be 8 bits, all the upper bits
> will be 0. So you can unroll the 8 iterations of the binary division
> loop to compute each of the bit, instead of going with a loop through
> the 32 iterations of the standard software division.
>
>> With reference to my earlier email, I wasn't really suggesting listing to 8KHz square waves (bandlimited or not) - it's just that I couldn't really grasp how such an algorithm would manage to degrade correctly and only generate a couple of harmonics in an extreme case.
>
> Trust the maths :) At high frequency, the ratio between the "period"
> of the BLEP ripples and the oscillator frequency will get close to 1.
> The 8kHz band limited square wave will be a sine because the ripples
> of the BLEPs will overlap each other exactly.
>
>> I thought Olivier's suggestion of using BLEP for low frequencies and something else for highs was insightful. BLIT/BLEP algorithms have a computational cost that increases with frequency. This would make it a good match for something like additive synthesis, which has a computation cost that *decreases* with frequency. So use each for the the part of the spectrum it's best at - it's an interesting idea. Of course, there's extra complications in using two algorithms, and perhaps that outweighs the benefits on specific hardware.
>
> Sadly, you can't do real sync or PWM with additive synthesis.
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