[sdiy] Non-inverting output buffer

[ASSI]

On Tuesday 27 April 2010, David G. Dixon wrote:
> Can you state, for dummies like me, just exactly what would
> constitute a "capacitive load" which might (or definitely would)
> cause oscillation of an unadorned follower?

Anything where the voltage lags the current a significant amount.  The 
simplified and hence "not even wrong" explanation for this: opamp 
slews the output due to whatever happens on the input, but it 
doesn't see anything moving on the feedback input (yet).  Tries to 
slew more and then finally finds it has gone too far and does the same 
thing the other direction.  This produces very hot opamps and strange 
measurement results until you realize you've got fuzzy lines on the 
scope (if you happen to have one connected - been there, done that).

Proper frequency compensation of the voltage follower is interestingly 
quite complicated if you want fast settling (this shouldn't be much of 
a problem for the application discussed here).  I recommend 
"Operational Amplifiers" by Jiri Dostal (however I don't know how good 
the english translation is), which explains the "why" and "how" in 
detail without cutting any crucial corners and with plenty of 
practical tips.  The cheap and cheerful alternative is "Op Amps for 
Everyone" by Rob Manchini - get document SLOD006 from TI - which 
discusses this specifically in section 7.4 (but doesn't go into nearly 
as much detail as Dostal).  "OpAmp Applications" by Walt Jung - grab a 
copy at Analog Devices - has this discussion in section 6.2, again 
from a slightly different angle.

> E.g., what would the input capacitance of the load have to be, how
> small would the load impedance have to be, and how would this
> capacitance have to be presented relative to the load (in series,
> in parallel, either, etc).

Output to ground is used for analysis, but in reality you look at a 
complex impedance that is only partly capacitive.  For highspeed 
opamps the datasheet will usually tell you how much capacitance can be 
tolerated at the output (or equivalently how much phase margin you 
need to leave).  You can test this by putting a square wave on the 
input and observing the overshoot, ringing and creep on the output.  
You'll want to see at most three "wiggles" for any normal amplifier 
and a small aperiodic overshoot for precision amps.


Back to the circuit from the OP:

The 33pF cap closes the feedback loop for high frequency and also 
compensates the parasitic capacitance of the summation point (the [-] 
input), the corner frequency is determined together with the feedback 
resistor.  Depending on your layout and where that introduces 
additional parasitic caps you may not even need an explicit cap there, 
but it certainly needs to be larger when the feedback resistor gets 
smaller (there's another reason not to short the feedback loop in a 
real circuit).  R2 ensures the real (resistive) component of the load 
as seen by the opamp output is never less than R2, the R1 feedback is 
effective at low frequency.  Since R2 is inside the feedback loop, 
there is no gain error introduced by R2 as long as the opamp can drive 
the additional voltage R2*I_L = R2/R_L*V_in.  In other words, don't 
design for rail-to-rail output (TL07x is not good for that anyway) and 
keep R2 much smaller than R_L.  For series compensation of capacitive 
loads this resistor would normally be outside the feedback loop, so 
all it really does here is limiting the slew rate and isolating the 
feedback cap from the load, the main compensation is provided by the 
feedback cap.


Achim.
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