[sdiy] SSM2164 Questions

cheater cheater cheater00 at gmail.com
Thu Apr 15 23:29:39 CEST 2010


can't you just label the jack 'bandwidth' :-))

D.

On Thu, Apr 15, 2010 at 23:15, Neil Johnson <neil.johnson97 at ntlworld.com> wrote:
> Hi Stewart,
>
> Stewart Pye wrote:
>>
>> The Electrical Characteristics don't tell any more than this:
>> ground referenced –33 mV/dB control port
>>
>> and the single supply example states: 0dB gain at Vc = V+/2.
>>
>> This leads me to believe the following when using a +/-15V supply...
>> 1. There is 0dB of gain when the control port is at 0V.
>> 2. Gain increases 1dB for every 33mV more negative the control voltage is
>> (eg -99mV would be +3dB gain)
>> 3. Gain decreases 1dB for every 33mV more positive the control voltage is.
>> 4. The maximum attenuation is quoted as -100dB, so to get this you'd need
>> 100 * 33mV = +3.3V
>> 5. The maximum gain is quoted as +20db, so to get this you'd need 20 *
>> 33mV = -0.66V
>> 6. In normal synthesizer use such as a VCF you'd use an inverting summing
>> stage for your CV inputs and add an offset so that with a 0V CV input you'd
>> get maximum attenuation (somewhere around +3.3V), and gain would increase
>> with increasing CV input voltage.
>>
>> For those that have played with these chips do these seem like reasonable
>> conclusions?
>
> Yeah, that's a good start.   Some practical examples with the 2164 can be
> found here:
>
> http://www.milton.arachsys.com/nj71/index.php?menu=2&submenu=0&subsubmenu=0
>
> The exact relationship between external CV and voltage applied to the 2164
> control port depends on the type of function.  For example, in the VCF the
> frequency response needs an inverter as you say, while the resonance needs a
> non-inverting buffer to give the correct control law (increasing CV gives
> increasing Q).
>
> Cheers,
> Neil
> --
> http://www.njohnson.co.uk
>
>
>
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