[sdiy] fast opamp with low offset

[cheater cheater]

Hi David,

> All good ideas, Jerry.  I think I've tried 'em already, but I can't really
> remember. (...)
>
> I was also thinking that (...)
>
> Another
> thing I thought of was (...)
>
> oh, and one more thing I thought of was (...)
>
> (I feel like I'm chained to a rock with a big old bird pecking away at my
> innards, and every day I wake up and it starts all over again...)

Sounds like you're losing track a bit :-) When I do research I find it
useful to have a journal. You might want to make a printout (physical
print, not a digital file! very important) of your current schematic,
exactly as it is on the breadboard, and then make a separate page in
the journal for each modification you try, give them numbers 1, 2, ...
. At the end of the journal have a table with 'modification number',
'glitch swing peak', 'swing area', 'swing peak as % of waveform Vpp',
'potential negative sides of modification' - this should help organize
thoughts.

Sometimes even stuff as simple as this is for you becomes very
difficult for me when I don't have it organized nicely :-)

HTH
D.

On Tue, Apr 6, 2010 at 19:08, David G. Dixon <dixon at interchange.ubc.ca> wrote:
> All good ideas, Jerry.  I think I've tried 'em already, but I can't really
> remember.  Probably worth trying them again!  I was also thinking that it
> might be good to increase the current flow through 2164 (by decreasing the
> size of the resistor on the input and increasing the size of the integrator
> cap).  Of course, the higher cap charge would require a longer discharge
> time, but it could be 2164 current biases that are messing me up.  Another
> thing I thought of was to put a resistor between the JFET + cap and the
> summing node, but to bring the 2164 directly into the summing node.  This
> way the 2164 will be somewhat isolated from the switch, but the resistor
> won't load the 2164...
>
> (I know neither of these will work, but I'll try 'em anyway... (defeatism at
> it's best!))

It's useful to try stuff! :-)

> The darndest thing is, I actually achieved about 0.03% tracking from 31.25Hz
> all the up to 32kHz with this beast on the breadboard under one condition,
> but couldn't reproduce it on the PCB.  There is some combination of stray
> breadboard capacitances which is allowing this thing to behave as it should,
> but I haven't figured out how to reproduce them...
>
>
>> Just a couple of thoughts,
>>
>> The action of the JFET discharging the cap may be inducing some current
>> flow
>> at the summing node that the integrator is responding to with high gain.
>> You might as an experiment add some resistance in series with the cap/JFET
>> and see what this does to the spike. Of course the resistance will effect
>> the wave shape, but this may help isolate/identify the mechanism
>> generating
>> the spike. Once you have the spike generation mechanism fully understood a
>> solution may present its self. Another experiment to try would be add
>> resistance into the 2164 current source feed into the integrator, the 2164
>> may be overreacting the shift in load, the resistance will have it
>> operating
>> at a higher voltage for the same current and if it is the spike source you
>> should see a change in the spike characteristics.
>
>
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