[sdiy] fast opamp with low offset

[Jerry Gray-Eskue]

Just a couple of thoughts,

The action of the JFET discharging the cap may be inducing some current flow
at the summing node that the integrator is responding to with high gain.
You might as an experiment add some resistance in series with the cap/JFET
and see what this does to the spike. Of course the resistance will effect
the wave shape, but this may help isolate/identify the mechanism generating
the spike. Once you have the spike generation mechanism fully understood a
solution may present its self. Another experiment to try would be add
resistance into the 2164 current source feed into the integrator, the 2164
may be overreacting the shift in load, the resistance will have it operating
at a higher voltage for the same current and if it is the spike source you
should see a change in the spike characteristics.

-----Original Message-----
From: synth-diy-bounces at dropmix.xs4all.nl
[mailto:synth-diy-bounces at dropmix.xs4all.nl]On Behalf Of David G. Dixon
Sent: Tuesday, April 06, 2010 12:40 AM
To: 'David G. Dixon'; 'ASSI'; synth-diy at dropmix.xs4all.nl
Subject: Re: [sdiy] fast opamp with low offset


> My latest simulations suggest that simply connecting a 3.3nF cap from the
> integrator summing node to ground will reduce the glitch spikes from +/- 1
> to 2V to +/- 20mV ...(snip)...

Well, filtering the JFET switch output at the integrator summing node was a
total and complete failure.  In fact, attaching any capacitor large enough
to have an effect on the 2164 output caused it to go completely berserk.

Interestingly enough, connecting a diode to ground to reduce the spike also
had no significant effect.  I'm starting to wonder whether the problem with
using 2164 as a current source is related to the JFET glitch at all, or
whether it is not just a general aversion to capacitive loads.

I'm open to any and all ideas at this point.

Boy, do I wish I had a real SPICE model of this damn chip!

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