[sdiy] fast opamp with low offset

[David G. Dixon]

> My latest simulations suggest that simply connecting a 3.3nF cap from the
> integrator summing node to ground will reduce the glitch spikes from +/- 1
> to 2V to +/- 20mV ...(snip)...

Well, filtering the JFET switch output at the integrator summing node was a
total and complete failure.  In fact, attaching any capacitor large enough
to have an effect on the 2164 output caused it to go completely berserk.

Interestingly enough, connecting a diode to ground to reduce the spike also
had no significant effect.  I'm starting to wonder whether the problem with
using 2164 as a current source is related to the JFET glitch at all, or
whether it is not just a general aversion to capacitive loads.

I'm open to any and all ideas at this point.

Boy, do I wish I had a real SPICE model of this damn chip!