[sdiy] fast opamp with low offset

[David G. Dixon]

This is what Horowitz and Hill (2nd ed.) have to say about FET charge
injection:

"During turn-on and turn-off transients, FET analog switches can do nasty
things.  The control signal being applied to the gate(s) can couple
capacitively to the channel(s), putting ugly transients on your signal.  The
situation is most serious if the signal is at high impedance levels....  The
handsome transients are caused by charge transferred to the channel, through
the gate-channel capacitance, at the transitions of the gate.  The gate
makes a sudden step from one supply voltage to the other..., transferring a
slug of charge Q = C_GC[V_G(finish) - V_G(start)].  C_GC is the gate-channel
capacitance, typically around 5pF.  Note that the amount of charge
transferred to the channel depends only on the total voltage change at the
gate, not on its rise time.  Slowing down the gate signal gives rise to a
smaller-amplitude glitch of longer duration, with the same total area under
its graph.  Low-pass filtering of the switch's output signal has the same
effect...."

They give the impression that there is really no cure for this problem; only
treatment of the symptoms.  Low-pass filtering of the switch output looks
like the most straightforward approach.

My latest simulations suggest that simply connecting a 3.3nF cap from the
integrator summing node to ground will reduce the glitch spikes from +/- 1
to 2V to +/- 20mV.  Apparently, the on-resistance of the switch itself is
enough to give the requisite RC time constant.  A small resistor may also be
added in series with the switch, without loading the 2164 expo current
source.  Interestingly, according to my simulations, adding a resistor
between the switch and the summing node actually improves HF tracking (even
though it adds to the overall on-resistance of the switch).  I have as yet
to figure this out.  In the meantime, I've got some breadboarding to do!


> May I suggest again to fight the problem rather than the symptoms?
> 
> You say the problem is the charge injection from the reset switch or
> more precisely the feedback reaction of the 2164 to a fast voltage
> change at it's output.
> 
> This might for instance be countered by using a different switch
> (JFET, or perhaps a modern analog switch with low charge injection),
> clamping the summing node during the reset or by draining the cap to a
> real instead of virtual ground (or an op-amp produced copy thereof) or
> by canceling the charge injection via a replica switch.
> 
> You could also try to isolate the 2164 via another current mirror, but
> the mirror would have to be very precise over some decades of current.
> Your I-V-I idea does that in a way, but as you said you'd need
> insanely speced components for it to work correctly.