[sdiy] Discrete buffer distortion

[Antti Huovilainen]

Hi

I've lately been simulating some discrete circuits in spice. One effect 
has me stumped: when using simple NPN / JFET follower with active high 
impedance load (to keep Vbe / Vgs constant), the distortion seems heavily 
influenced by frequency and source impedance. The PSU voltage also plays a 
large role, as the distortion seems to be inversely related to PSU voltage 
(Vcb / Vdg in particular).

What is the cause of this distortion? I'm guessing it has something to do 
with parasitic capacitance of the transistor, but why does it show up as 
distortion and not high cut? And why is the effect so huge? (1% THD for 20 
kHz 1V RMS signal with J201, +- 4.5V suply and 1 MOhm source impedance).

Antti

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