[sdiy] Op Amp Buffer stability

[Justin Owen]

Hello,

I'm on a bit of a power supply stability mission at the moment.

I'm using an Op Amp buffer/voltage follower to supply VCC/2 (10K Resistor from VCC and 10K Resistor from Ground - both to Non Inverting Input).

I've noticed that putting the positive side of a 10uF electrolytic cap on the Inverting input and running the Negative side of the cap to Ground has drastically smoothed the output of the buffer.

Is there a reason why I *shouldn't* be doing this? I can't find an example of anyone using this on a buffer anywhere - so I'm a little cautious.

Oh - any other low component count, power supply stability tips would be most welcome.

FWIW VCC is 9 Volt.

Thanks all,

Justin