[sdiy] Dual oscillator cores?

[cheater cheater]

Hi guys,
I was wondering if a design like this was tried somewhere already.. it
seems basic enough that someone should have thought of it before :-)
I'm not an expert at any rate, but I think it could work well to
remove HF problems existent in some popular approaches at designing
oscillator cores..

Saw core. Two accumulators instead of one - call them A and B. Both
are empty at the beginning. They both go out through one JFET each,
that JFET works as a voltage controlled switch. They also both have
their 'inputs' connected to one voltage controlled switch made out of
a JFET each. (so two parallel chains of JFET -> Acc -> JFET). When you
turn on the oscillator, accumulator A's input and output JFET are on
and the accumulator starts being loaded. Each accumulator has one
comparator each. When Acc A reaches the trigger level for comparator
A, two things happen: 1. the input switch A is turned off 2. The input
switch B is turned on 3. The output switch A is turned off. 4. The
output switch B is turned on. At that point accumulator B is at level
0 and starts moving up towards comparator B's trip level. 5.
Accumulator A gets drained. There is no delay while it's being
drained, because it's B that is outputting at that point.

Of course accumulator A becomes drained long before B reaches its trip
point. Once B reaches its trip point, it gets swapped with A again.

What are the main problems with such an approach that you guys can see?

Thanks a lot
Damian