[sdiy] 2164 expo VCO tracks!

[David G. Dixon]

After a "somewhat" premature announcement last week concerning the
completion of my 2164 expo VCO, I found several mistakes on my PCB, and made
a few small design changes.  My "Rev. A" board is now perfect.  I notice,
however, that the saw-core circuit does not behave exactly like the
simulation, insofar as a significantly larger comparator time constant is
required to fully reset the integrator.  I'm using an RF JFET, 2N5485, as I
did not have access to the ones Ian Fritz suggested (2N4391 or PN4391).
Simulations suggested that the 5485 would be ever so slightly faster, in any
case, even though it has significantly larger on-resistance.  Simulations
also suggested that about 560ns would be sufficient to fully reset the
integrator with the parts I'm using, but I found that about 1.5us is
required, and even then the comparator is only getting to within about 50mV
of ground.  I'm also clamping the comparator to one diode drop above ground
during reset, so I don't think that the comparator (1/4 of a lowly TL074) is
the rate-limiting step.  That's the bad news...

The good news is, the VCO is (so far as I can tell by probing around with my
hot fingertips at 3520Hz) perfectly temperature compensated (the frequency
didn't budge), and optimum values of the tempco voltage and CV summer gain
are exactly what I predicted them to be (289.5mV and 54.64%, respectively).
Here is the tracking, based on 440Hz at 3.000V CV, after high-frequency
trimming:

1.000V   110Hz
2.000V   220Hz
3.000V   440Hz
4.000V   879Hz
5.000V  1760Hz
6.000V  3520Hz

The tracking begins to fall apart above about 6000Hz.  Replacing one quad
opamp with a better one and using the proper JFET would tighten it up, but
this is better than 0.1% tracking within the "piano" frequency range.  The
waveforms are also really nice (just the tiniest glitchy spike in the
triangle and the sine, totally inaudible).

I will be sending out all the details to my devoted fans later this evening,
after I run a few errands.