[sdiy] VCO Tuning goals

[cheater cheater]

Can't you get around the cap discharge time by using two capacitors
and switching between them? One is getting discharged while the other
one is loading?

D.

On Sat, Oct 3, 2009 at 7:52 AM, David G. Dixon <dixon at interchange.ubc.ca> wrote:
>> David, with regards to the integrator reset 'problem': are you
>> referring to the error introduced by the comparator being off by some
>> percentage, say A? In that case the output frequency will be 1/A f'
>> where f is the frequency we're trying to get. Which in turn means that
>> a simple offset voltage fed into the linear voltage input in the EC
>> would be good enough I guess?
>> And if so, then it's a problem only in the (quite probable) situation
>> when you want to run multiple oscillators from the same EC.
>>
>> Then there could be the consideration of the switching lag in the
>> comparator, which I think might introduce a linear frequency shift and
>> then a small exponential freq shift if the switch speed depends on the
>> voltage across the comparator.. but that can't be bothersome until
>> we're in HF range, right? Definitely not in the audible range... I
>> think.. but that's just guessing, not backed up with any real
>> knowledge or experience =)
>
>
> The comparator switching lag is mostly eliminated by putting a very small
> (10p or so) cap across the positive feedback loop.  I believe that the bulk
> of the HF problem is then primarily JFET shunting time.  JFETs have on
> resistances of tens of ohms, so they take some time to discharge the cap.
> In a conventional expo converter, there is also a bulk transistor resistance
> issue, which I don't fully understand, but I'm trying to get a handle on it.
> Ian Fritz is giving me pointers, but so far I have had no luck whatsoever
> simulating his expo converter in Multisim, so I don't know...
>
>