AW: AW: [sdiy] AD/DA schematics? quantizers,etc

[Dave Manley]

Dan Snazelle wrote:
> also...i do NOT know if i am running this at the correct sample rate
>
> i have had NOTHING but trouble finding a clock that is both stable and will go high enough
>
>   
The ADC you selected uses a SAR (Successive Approximation Register) 
which requires *eight* clocks per conversion - from the time you assert 
Start, until EndOfConversion occurs, takes 8 clock ticks.  So if you 
want to sample the input at a 1 KHz rate, you need an 8 KHz clock.  
Perhaps this is why you think it needs such a high clock rate.

http://en.wikipedia.org/wiki/Successive_Approximation_ADC

You could always run the ADC at the same (high) speed and then just 
periodically (slowly) transfer the output to the DAC.  You need to be 
careful if you do this not to run afoul of metastability.   There are 
very specific design rules you need to follow when transferring data 
from one clock domain to the other.  This will require some flops, and 
holding registers to do it cleanly.

Explore the links at the end of this article for more info:

http://en.wikipedia.org/wiki/Metastability_in_electronics

-Dave