[sdiy] Opinions on input protection

[Joe Grisso]

On Thu, Mar 26, 2009 at 12:04 PM, Scott Nordlund <gsn10 at hotmail.com> wrote:
>
> I guess in general it would be a good idea to test these things before deploying them, though it had really never occurred to me before.  In some cases there are expensive or irreplaceable components to be protected, and I wouldn't want to leave that to an untested circuit.

Yeah, like a 200MHz ARM9 in a BGA package... that would suck to fry an
input pad on it.

> I'm not sure how necessary it would be to protect an inverting amplifier input, as the op amp will clip (and limit the current draw) but shouldn't be harmed unless the inverting input pin exceeds the supply voltages (which would require a severe overload).  Other summing node inputs (like OTAs) should be easier to damage.  Maybe in this case the input resistor could be split, with reverse-parallel diodes somewhere "inside" to limit the maximum input current?

For op-amps, it's not a big deal. The general case I'm applying here
is something like this:

[Trigger from EG, gate from KB, etc] -> [Input Circuit] -> [MCU or
other digitalia]

Where the triggers can be anywhere from 0-15V in some cases, and the
MCU is running at 3.3V or less.

I usually use an input similar to what Yves Usson uses on his ADSR
circuit - basically a diode that's reverse biased on the gate input to
filter out any negative voltages, then a double NPN CE buffer that
acts as a switch. Instead of just buffering though, I usually have 2
lower voltages available in my designs - a 5V and a 3.3V. So, I take
the first transistor and use 5V as Vcc, and 3.3V as Vcc on the second
transistor. It drops pretty well, and I only get about 0.3-0.4V of
undershoot/overshoot during switching transients - they only last
300nsec or so. However, I do have this nasty tendency to oversimplify
and want to reduce the circuit to a minima at times, so I wanted to
get others opinions... hence the message. I like to see what other
folks on the list are doing.

-- 
Joe Grisso
Detachment 3 Engineering