[sdiy] from timing to circuit /was SRAM versus DRAM
Dave Manley
dlmanley at sonic.net
Wed Jun 24 18:01:43 CEST 2009
Dan Snazelle wrote:
> the more i look at this, the more it is starting to make sense.
>
> am i correct in thinking that i do not need the tri state buffer since my adc already has tri-state outs? (is that what ADC_OE is for in the timing diagram?
>
I haven't had a chance to look at your ADC datasheet, but if it has a
tri-state output enable then you won't need the buffer.
> the only thing on your diagram that i cant figure out is what RAM_DO is. is this chip enable?
>
The RAM_DO is just showing what the RAM's Data Output bus is doing. This
is the I/O bus of the ram, but just showing
the output side of it. It shows when the RAM is driving the bus.
> beyond reading the timing diagram my main fear is this
>
> how on earth do you TEST the 4017 or other chip to SEE if you have the phases correct?
>
If you have a two channel scope, you can trigger the scope with the ph0
output, and then look at the others one at a time. If
your scope has an external trigger input, you can trigger the scope with
ph0 (or another signal) and look at two other signals
with your two input channels.
> other than just hooking everything up and using trial and error?
>
> you mentioned using And/or gates as well which adds another unknown variable.
>
> how do you know which bits to OR?
>
I suggested ORing phase 5 and phase 6 to generate a wider pulse. There
are many ways to control an SRAM when
you look at the combination of R/W, CS and OE. The key thing you need
to watch out for is 'contention' on the
data bus. This happens when two different devices try to drive the bus
at the same time. For example, if the ADC
output is enabled and the RAM is in READ mode, you will have contention,
the two devices will be fighting each
other to control the bus. This burns power and can damage devices. The
critical time in this circuit is when the
RAM databus turns off, and the ADC output turns on (and vice versa).
During these times there can be contention.
You need to look at the timing characteristics of these devices to see
if this is a problem. I can go into more
detail later. Or we could use the multi-phase clocks to guarantee there
is never any contention, this will require
a little bit more logic.
> I suppose what I am asking is since obviously not all of the outputs from the 4017 will plug
> into a dual trace scope, do you just keep comparing the Clock to each individual out?
>
> this has been what has always kept me away from building complex logic...a real gap in my
> knowledge and experience. but the way you numbered your timing counter made it much easier to
> understand what NEEDS to happen. now the battle is getting it to work.
>
Most digital circuits eventually comes down to a datapath and control
logic. The control logic is made very simple
if you have a multiphase clock. Many processors use multiphase clocks
internally for the control logic.
> also i am assuming we are talking about a very fast clock since so much has to happen in such a small amount of time right?
>
The Polyphony uses a very fast clock because the ADC they used requires
44 clock ticks for conversion. Their circuit divides the clock
by 5 and then again by 10. This gives a divide by 50, with the multiple
clock phases coming off the divide by 10. You need to look at
your ADC and see how many clocks it needs to complete a conversion.
Then we can modify this circuit to work with your ADC. The
key idea here is the high speed clock is ticking 50 times per
conversion, and the control logic spaces out control pulses across these
50 ticks, to sequence the data in and out of the various parts.
> and when you say increase the size of the address counters, i am hoping this just means adding more counters as there will just be more address lines? the chip i am looking at has 14 address pins.
>
Most counter chips have a way of connecting multiple devices to form
wider counters. Take a look at the data sheet for the '193 to see how
it is done.
> i am looking at this chip:
>
> AS6C62256-55PCN
>
> http://www.jameco.com/webapp/wcs/stores/servlet/ProductDisplay?langId=-1&storeId=10001&catalogId=10001&productId=1927414&
>
At a glance that looks fine, I was looking at the Cypress part, as I
have had good experience with Cypress in the past.
http://www.jameco.com/webapp/wcs/stores/servlet/ProductDisplay?langId=-1&storeId=10001&catalogId=10001&productId=391793&
>
> sorry for all the questions
>
>
>
>> Dan,
>>
>> For an octal tri-state buffer look at a 240, 241, 540, 541, etc
>> For an octal latch look at 273, 573, 574, etc
>>
>> The timing circuit in the Polyphony article is easy to modify because it
>> uses a CD4017 to generate a 10 phase clock. It is easy to pick
>> different phases, invert a phase, and/or to 'OR' multiple phases
>> together to generate timing pulses to control everything.
>>
>> Hook up the ram like this:
>>
>> 1. ADC digital output is connected to octal-tristate buffer inputs
>> 2. octal tristate buffer outputs connected ram data i/o bus
>> 3. ram data i/o bus connected to octal latch data input
>> 4. octal latch data output connected to DAC digital input
>>
>> Otherwise the circuit is nearly identical to the one in the article.
>>
>> Here's an example timing, where ph0->ph9 are the 10 output clock phases
>> from the CD4017, all the
>> phases aren't used, but are shown:
>>
>> (use Courier font to make sense of the following)
>>
>> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
>> clock _/0\_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\_/9\_/0\_/1\_/2\_/3\_/4\_
>> ___ ___
>> ph0 _/ \___________________________________/ \_______________
>> ___ ___
>> ph1 _____/ \___________________________________/ \___________
>> ___ ___
>> ph2 _________/ \___________________________________/ \_______
>> ___ ___
>> ph3 _____________/ \___________________________________/ \___
>> ___ ___
>> ph4 _________________/ \___________________________________/
>> ___
>> ph5 _____________________/ \___________________________________
>> ___
>> ph6 _________________________/ \_______________________________
>> ___
>> ph7 _____________________________/ \___________________________
>> ___
>> ph8 _________________________________/ \_______________________
>> ___
>> ph9 _____________________________________/ \___________________
>> ___ ___
>> addr_clk _____/ 1 \___________________________________/ 1 \___________
>> _____________________________________________________________
>> addr _____X_______________________________________X_______________
>> ___ ___
>> latch_clk _____________/ 3 \___________________________________/ 3 \___
>> _____________________________________________________________
>> latch_data_____________X_______________________________________X_______
>> _____________________ _______________________________
>> adc_oe \__5+6__/
>> _______
>> adc_data ----------------------------------------------------
>> _____________________ ___________________________________
>> ram r/wb \_5_/
>> ________
>> ram_oeb _____________________/ 5+6 \______________________________
>> _____________________ _______________________________
>> ram_do _____________________>-------
>> Notes:
>>
>> 1. on the positive edge of ph1 the address counters increment, start ADC
>> conversion
>> 2. the ram is almost always in read mode
>> 3. on the positive edge of phase 3, latch the ram output data into the
>> DAC data latch
>> 4. on phase 5 and phase 6 disable the ram data outputs, enable the ADC
>> tristate buffer
>> 5. ADC converted data is now on the ram input pins, pulse ram r/w low,
>> write data to ram
>>
>> If you use a 32Kx8 ram and use the same timing in the Polyphony article,
>> the max delay goes up to around 1.3 seconds. To get this bigger delay,
>> you will need to increase the size of the address counters (U14, U15,
>> U16) to support the bigger address bus on the 32Kx8 ram. It is easy to
>> chain together the '193 counters, so this shouldn't be any problem.
>>
>> If you are willing to do some extra circuitry, you could make this a
>> multi-tap delay without too much trouble.
>>
>> -Dave
>>
>> Dan Snazelle wrote:
>>
>>> i am currently using
>>>
>>> ADC0820 and DAC0800
>>>
>>> i have a few other ADC's here if that would make things easier
>>>
>>> i also have some DAC0808's
>>>
>>> i have an order coming soon with some TTL octal latches (i hope i bought the right ones)
>>>
>>> 74hc573's i think
>>>
>>> i dont know if i have a tri state buffer
>>>
>>> but i can order whatever is needed
>>>
>>> this would be a lot of fun to get working!!
>>>
>>> i think my main hurdle/fear is that I dont have a very good handle on how to turn a timing diagram into a working circuit
>>>
>>> i know that in theory what you do is take the clock and using logic and a counter, send it to different parts of the circuits at different times
>>> Right? (to turn some on, some off, and to direct the INS and OUTS of the I/O pins. but figuring out when and how has always seemed very
>>> hard to me)
>>>
>>> i already have the HM6264 which is a
>>>
>>> 8192x8 SRAM chip
>>>
>>> so that might work to start
>>>
>>> i really appreciate all the help..i know this topic has been going on for awhile now
>>>
>>> ----------------------------------------
>>>
>>>> Date: Tue, 23 Jun 2009 20:07:59 -0700
>>>> From: dlmanley at sonic.net
>>>> CC: synth-diy at dropmix.xs4all.nl
>>>> Subject: Re: [sdiy] SRAM versus DRAM
>>>>
>>>> Dan forwarded me the schematic. It is very easy to convert to use a
>>>> SRAM with multiplexed data pins. Looking at Jameco, I see a bunch of
>>>> parts, 32Kx8, 128Kx8, in DIP packages that are less than 4 bucks. To
>>>> modify the circuit to work with a modern SRAM will require adding an
>>>> octal latch, an octal tri-state buffer and some control logic. If the
>>>> A/D has tri-state outputs the tri-state buffer can be eliminated, and
>>>> if the D/A has a latch, the octal latch can be eliminated. I'll try to
>>>> post the timing later tonight.
>>>>
>>>> Dan, what ADC and DAC are you planning on using?
>>>>
>>>> -Dave
>>>>
>>>>
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