[sdiy] SRAM versus DRAM

[Dan Snazelle]

i am currently using

ADC0820 and DAC0800

i have a few other ADC's here if that would make things easier

i also have some DAC0808's

i have an order coming soon with some TTL octal latches (i hope i bought the right ones)

74hc573's i think

i dont know if i have a tri state buffer

but i can order whatever is needed

this would be a lot of fun to get working!!

i think my main hurdle/fear is that I dont have a very good handle on how to turn a timing diagram into a working circuit

i know that in theory what you do is take the clock and using logic and a counter, send it to different parts of the circuits at different times
Right? (to turn some on, some off, and to direct the INS and OUTS of the I/O pins. but figuring out when and how has always seemed very 
hard to me)

i already have the HM6264 which is a 

8192x8 SRAM chip

so that might work to start

i really appreciate all the help..i know this topic has been going on for awhile now







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----------------------------------------
> Date: Tue, 23 Jun 2009 20:07:59 -0700
> From: dlmanley at sonic.net
> CC: synth-diy at dropmix.xs4all.nl
> Subject: Re: [sdiy] SRAM versus DRAM
>
> Dan forwarded me the schematic. It is very easy to convert to use a
> SRAM with multiplexed data pins. Looking at Jameco, I see a bunch of
> parts, 32Kx8, 128Kx8, in DIP packages that are less than 4 bucks. To
> modify the circuit to work with a modern SRAM will require adding an
> octal latch, an octal tri-state buffer and some control logic. If the
> A/D has tri-state outputs the tri-state buffer can be eliminated, and
> if the D/A has a latch, the octal latch can be eliminated. I'll try to
> post the timing later tonight.
>
> Dan, what ADC and DAC are you planning on using?
>
> -Dave
>
>
> mark verbos wrote:
>> I think the point is that you have a voltage controlled master clock
>> that speeds up/slows down the counter to change the delay time.
>> Couldn't you use 8x4164s with the same timing logic as in one of the
>> other ones that used it?
>>
>> mark
>>
>>
>>
>>
>>
>> On Jun 23, 2009, at 9:29 PM, John Luciani wrote:
>>
>>> On Tue, Jun 23, 2009 at 9:24 PM, Dan
>>> Snazelle wrote:
>>>>
>>>> i know a lot of digital delays use the 2164 DRAM (peavey, electro
>>>> harmonix and MXR digital delay)
>>>> which is why before I saw the polyphony digital delay project which
>>>> calls for SRAM (4k x 1 bit, 8 of them) I had thought DRAM was the
>>>> way to go in a digital delay.
>>>
>>> How old is the Polyphony article? I would use a uC that has a DRAM
>>> controller and then
>>> the refresh issue is solved. It also gets you control of ADCs and DACs.
>>>
>>> Using SRAM is probably going to be very expensive.
>>>
>>> (* jcl *)
>>>
>>>
>>> --
>>>
>>> You can't create open hardware with closed EDA tools.
>>>
>>> http://www.luciani.org
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