[sdiy] SRAM versus DRAM

[Dave Manley]

Dan forwarded me the schematic.  It is very easy to convert to use a 
SRAM with multiplexed data pins.  Looking at Jameco, I see a bunch of 
parts, 32Kx8, 128Kx8, in DIP packages that are less than 4 bucks.  To 
modify the circuit to work with a modern SRAM will require adding an 
octal latch, an octal tri-state buffer and some control logic.  If the 
A/D has  tri-state outputs the tri-state buffer can be eliminated, and 
if the D/A has a latch, the octal latch can be eliminated.  I'll try to 
post the timing later tonight.

Dan, what ADC and DAC are you planning on using?

-Dave


mark verbos wrote:
> I think the point is that you have a voltage controlled master clock 
> that speeds up/slows down the counter to change the delay time.
> Couldn't you use 8x4164s with the same timing logic as in one of the 
> other ones that used it?
>
> mark
>
>
>
>
>
> On Jun 23, 2009, at 9:29 PM, John Luciani wrote:
>
>> On Tue, Jun 23, 2009 at 9:24 PM, Dan 
>> Snazelle<subjectivity at hotmail.com> wrote:
>>>
>>> i know a lot of digital delays use the 2164 DRAM (peavey, electro 
>>> harmonix and MXR digital delay)
>>> which is why before I saw the polyphony digital delay project which 
>>> calls for SRAM (4k x 1 bit, 8 of them) I had thought DRAM was the 
>>> way to go in a digital delay.
>>
>> How old is the Polyphony article? I would use a uC that has a DRAM
>> controller and then
>> the refresh issue is solved. It also gets you control of ADCs and DACs.
>>
>> Using SRAM is probably going to be very expensive.
>>
>> (* jcl *)
>>
>>
>> -- 
>>
>> You can't create open hardware with closed EDA tools.
>>
>> http://www.luciani.org
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