[sdiy] SRAM versus DRAM

[Dan Snazelle]

i suppose i could/might do that

i will maybe take a look at the peavey schematic again and try to dissect what is going on with the logic

thanks






----------------------------------------
> CC: subjectivity at hotmail.com; synth-diy at dropmix.xs4all.nl
> From: mverbos at earthlink.net
> To: jluciani at gmail.com
> Subject: Re: [sdiy] SRAM versus DRAM
> Date: Tue, 23 Jun 2009 21:41:33 -0400
>
> I think the point is that you have a voltage controlled master clock
> that speeds up/slows down the counter to change the delay time.
> Couldn't you use 8x4164s with the same timing logic as in one of the
> other ones that used it?
>
> mark
>
>
>
>
>
> On Jun 23, 2009, at 9:29 PM, John Luciani wrote:
>
>> On Tue, Jun 23, 2009 at 9:24 PM, Dan
>> Snazelle wrote:
>>>
>>> i know a lot of digital delays use the 2164 DRAM (peavey, electro
>>> harmonix and MXR digital delay)
>>> which is why before I saw the polyphony digital delay project which
>>> calls for SRAM (4k x 1 bit, 8 of them) I had thought DRAM was the
>>> way to go in a digital delay.
>>
>> How old is the Polyphony article? I would use a uC that has a DRAM
>> controller and then
>> the refresh issue is solved. It also gets you control of ADCs and
>> DACs.
>>
>> Using SRAM is probably going to be very expensive.
>>
>> (* jcl *)
>>
>>
>> --
>>
>> You can't create open hardware with closed EDA tools.
>>
>> http://www.luciani.org
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>