[sdiy] More about IC design

[Greg James]

Paul,
I really appreciate the time you take to share this info. I learn a lot,
especially about the pragmatic side of things. Thanks.
-Greg

-----Original Message-----
From: synth-diy-bounces at dropmix.xs4all.nl
[mailto:synth-diy-bounces at dropmix.xs4all.nl] On Behalf Of Paul Schreiber
Sent: Saturday, July 11, 2009 10:53 PM
To: Robin Whittle; Synth DIY
Subject: [sdiy] More about IC design

Many ICs (especially digital ones) have specific "hooks" in the hardware in 
order to aid testing. "Testing" can be:

a) reduce testing time or complexity of the tester HW/SW (testers can be 
*millions* of dollars, a specific test 'head' can run $50,000 easy). In come

cases the IC designer has to take the test flow into account, and make 
allowances for what can be tested. Old saying "If you can't test it don't 
design for it."

Side note: when you see a typical IC data sheet, one naturally assumes all 
that stuff is tested, for every IC. Hardly. Typically 25% of all the 
parameters listed are actually tested. The others that are considered 
"second tier" are extensively *simulated* by what we call '4 corners': the 4

combinations of temperature and power supply voltage (hi/low Vcc and hi/low 
temp). The industry catch-phrase is "guarenteed by design" meaning the data 
sheet is 3X "worse" than any simultation ever saw.

What is actually tested? The answer is: what the IC designer thinks a 
customer would actually take the time to *measure themselves*. For an op 
amp, the #1 thing is DC offset, and the #2 thing is power supply 
consumption. #3 is input bias current and #4 is gain-bandwidth (which also 
can extrapotate to slew rate). Notice that this is 3 DC tests and 1 AC test.

Yes, you try to do as much in DC because it's *faster* and *cheaper*.

b) all really big digital ICs (especially now since silicon gates are so 
cheap, like 2,000 for 1 cent) have BIST (built-in Self test), JTAG 
boundary-scan (high speed serial buss that is like a logic analyzer inside 
the IC) or dedicated hardware (which then makes you wonder, what then tests 
the test hardware?).

The buzz-phrasefor digital ICs is "fault coverage". This means: how many 
"test vectors" (applications of a specific digital pattern to the IC) are 
need to test say 93% of all the gates in the IC? Because *no* chip is tested

100%, you would sit there all day. And in many cases, the number of test 
vectors *doubles* when you get to say 95% then want 97%.

Believe it or not, there is actual mathematical graphing theory that you can

*prove* that a specific set of test vectors will in fact cover xx% of a 
digital circuit. It was the *hardest* EE class I ever had in graduate 
school. It's called "Finite Automata Theory", here is just a *taste*:

http://en.wikipedia.org/wiki/Automata_theory

Of course, large IC design SW providers like Cadence and Mentor have SW that

will analyze your design and spew out reams of test vectors for you.

BTW: there are actually 2 'classes' of test vectors:

1 - a simple pass/fail
2 - being able to detect if a logic point is 'stuck at 0', 'stuck at 1' or 
'dead as a doornail' (not clocking) (fault *detection*)

Many large, fancy ICs (like Intel CPUs, nvidia GPUs, etc) have reduntant 
circuitry that "makes no sense" when you look at it but it's there to get 
the IC out the door. As the process geometries shrink smaller and smaller, 
gates are cheaper and cheaper (and a LOT faster) so slamming 2 or 3 
*million* 128-bit serial test vectors into an IC is no big deal. Back in the

'80s, I was doing test vectors for Tandy digital boards in the *100s* of 
vectors, all by hand (those were the good old days). Into a PDP-11. Using 
FORTRAN. ACK!

Sometimes just slamming test vectors is not "good enough", you start to 
resort to "wierdness", like this patent:

http://www.patentstorm.us/patents/6876220/claims.html

that is scanning the die for electromagnetic "patterns" and comparing them 
to KGD (Known Good Die) patterns. I have heard stories that people used to 
pour LCD fluid on analog die to look for "hot spots".

Paul S.

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