[sdiy] Re: IC parts binning

[Dave Manley]

LOL!  Hi Robin.  My comment was a gentle poke at Samppa's reputation
on the list, that's all.  I should have put a smiley there.

The subject is interesting, and a lot of effort and money is expended 
increasing
test coverage while reducing test time.  I've been working in the 
digital ASIC
field since the early 80's and am familiar with the basic techniques.  
Most ASICs
however don't hit the huge volumes that commodity parts do, so no doubt
there are many interesting test techniques I haven't seen.

The basic test for digital ICs consists of two phases: DC parametric and
then scan testing.  DC parametric testing consists of simple things like
powering up the device in a mode where it should consume little current,
and then measuring the current.  Often device faults will cause excessive
current to be drawn during this test.  This is a test that is simple to do,
runs quickly and detects gross faults.  Google IDDQ testing. Other 
parametric
tests verify the input switching thresholds, the output voltage and current
characteristics, high-impedance testing for tri-state IO, etc.  This IO 
testing
may be aided by the presence of a boundary scan ring controlled by
a JTAG interface.

The second phase, scan testing, consists of shifting automatically generated
test patterns into the device with all the internal flip-flops connected 
together
to form shift registers, putting the device into a functional mode, and then
shifting the new flip-flop state out, while shifting the next test 
pattern in.
This is commonly known as 'scan testing', the test patterns are generated
using Automatic Test Pattern Generation (ATPG) software.  Using this
methodology a very high fault detection rate is quickly acheived.

For digital devices with embedded ram, a methodology called Built
In Self Test (BIST) is used.  This technique wraps each internal ram
in a test circuit.  The circuit typically generates random patterns that
are written into the ram.  The ram is then read and a signature (like
a CRC) is calculated.  The signature of a good ram is known, so if
a different signature is detected, the ram is bad.  There are many,
many different ram test methodologies.  People have spent their careers
optimizing ram testing.

Many devices these days are not purely digital and contain analog
sections, PLLs, DACs and ADCs being the most common.  These
analog sections are tested separately.

I didn't mention that at the wafer level there are special test
structures built into the wafer and placed in between the die.
These structures allow the basic process parameters to be
measured.  Any parameter critical to the process can be
monitored in this way.  These process monitors will give
the data need to know whether the device will operate
across its operating environment (temperature, voltage,
and process variation).

You should also know that part of the design process is
to verify the operational timing of the device through simulation
and/or analysis.  The models used in this analysis are based
on test devices that have been built and characterized.  The
modeling allows the device to be tested, in simulation, or
analyzed with timing analysis programs at any operating
point - pick your voltage, temperature and process
minimum, typical, and maximum values and run an analysis.
If the device fails any of these corner cases, the design
will be modified so that it will operate in the specified
environment for that particular device.

Given all that, I would much rather be on the design side
than on the test side.  The test engineers are often in a high
pressure environment, and there is little glory to be had.

Hope this bit of writing excuses my lack of a smiley earlier.

And to answer your question, I had a double espresso about 6 hours
ago, and just recently a bottle of hard cider. :-)

Robin Whittle wrote:
> Hi Dave,
>
> I am not being a troll.
>
> I found Paul's article very interesting, particularly regarding the
> importance of testing time and therefore costs.
>
> Its one thing to design a CPU logically, another to figure out how to
> make it as a billion transistors on a single piece of silicon.  Then
> there is the daunting task of actually making them, for not too high
> a price.  But how do you test these things, at a single temperature,
> for a few seconds only, and be confident those which pass will, with
> a very high probability, go out into the world and work reliably for
> decades, at a range of different temperatures and voltages?
>
> How do they test EEPROM, FLASH cells etc to be sure they don't leak?
>
> I recall reading that Lattice GAL chips and the had the cells
> programmed and then by varying the power supply voltage it was
> possible to measure the threshold voltage of each cell precisely - by
> the power supply voltage changing the reference voltage of the sense
> amp.   Then, I recall, they would store this information and stash
> the wafers, or the packaged chips perhaps, for a few weeks.  Then
> they would measure the threshold voltages again and chuck out any
> chip in which a voltage drifted by too much.
>
> I guess with the mass gigabit FLASH chips they must have extra arrays
> to use in place of arrays with dead cells.  But how do they test for
> leakage on such a massive scale?
>
> Different testing problems would arise with simpler, but more
> finicky, analogue devices.  Digital stuff just has to race to the
> correct on or off voltage range in a given time.  Analogue stuff
> needs to be precise, stable, noise-free etc.
>
> All these chips are supposed to work reasonably reliably when running
> for years at temperatures way too hot to touch.
>
>
>   
>> Samppa Tolvanen wrote:
>>
>>     
>>> Basically the coolest post ever I've seen on SDIY.
>>>       
>> I'm trying to figure out how this is actually a troll.
>>
>> It looks like a compliment.
>>
>> But it has to be a troll.  Doesn't it?
>>     
>
> I wonder how much caffeine have you had in the last few days.
>
> Now I am arguably being a troll!  Or I would be if I hadn't admitted
> the possibility of such.
>
> But its the truth:  I do wonder why someone would see a
> straightforward, appreciative compliment as something quite the
> opposite.
>
>
>   - Robin
>
>
>
>
>