[sdiy] How droopy is too droopy in a S & H?

John Luciani jluciani at gmail.com
Mon Jan 26 19:25:14 CET 2009


On Mon, Jan 26, 2009 at 1:08 PM, mark verbos <mverbos at earthlink.net> wrote:
> I have been seduced by the Analog Devices SMP04 quad sample and hold chip.
> It has 4 independent S&H circuits with built in capacitors, in a 16 pin
> chip. I claims a "low droop rate" of 2 mV per Second. Doesn't that seem like
> a lot? How much does a normal sample & hold droop?

It seems quite good for a monolithic device which has internal caps.
Does the datasheet
mention how big the cap is?

If the cap is external it can be much larger which will give you a
much lower droop.

(* jcl *)

-- 

You can't create open hardware with closed EDA tools.

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