[sdiy] New TOG board: $0.02 needed

[Tim Ressel]

Follow-up: LM339s in 100 pieces: $0.20, or $0.60 per octave. I sense another board on the way....

--Tim (board-making fool) Ressel


--- On Wed, 1/7/09, harrybissell at wowway.com <harrybissell at wowway.com> wrote:

> From: harrybissell at wowway.com <harrybissell at wowway.com>
> Subject: Re: [sdiy] New TOG board: $0.02 needed
> To: "David Moylan" <dave at westphila.net>, madhun2001 at yahoo.com
> Cc: "sdiy" <synth-diy at dropmix.xs4all.nl>
> Date: Wednesday, January 7, 2009, 3:26 PM
> If its a TOG, wouldn't it be followed by digital
> dividers in most cases...
> making variable pulse width non-functional ?   The dividers
> would re-establish
> 50% duty cycle. There were some TOG that did not output a
> square wave... is
> this to emulate those cases ???
> 
> H^) harry
> 
> 
> 
> 
> 
> On Wed, 07 Jan 2009 13:25:47 -0500, David Moylan wrote
> > Perhaps if the serial data line could be made
> available and the code 
> > implemented a PIC could be programmed later to handle
> a CV to serial 
> > translation (I'd volunteer).  PWM would be great,
> but if it could 
> > only support static width I'd still be quite happy
> with that.
> > 
> > Dave
> > 
> > Tim Ressel wrote:
> > > --- On Tue, 1/6/09, David Moylan
> <dave at westphila.net> wrote:
> > > 
> > >> Any chance of varying the duty cycle
> dynamically?
> > > 
> > > Hmmm. There are 2 problems. The first is getting
> the data into the part.
> Are we talking about varying all 13 note at the same time
> and by the same
> amount? I assume we are. The second problem is more nasty.
> A variable PWM
> would have to be a number that varies from 1 to the max
> count of the counter
> minus 1. The problem is each note has a different max
> count. So if we try to
> load a single PWM number and use it on all the note
> counters, we get different
> PWMs for each note. The lowest note will get a full range
> while the highest
> note will only make it to 50%. I deem this too much to be
> useful.
> > > 
> > > So we need to load a different value for each
> note. This is possible. I'm
> note sure it will fit into the current CPLD family I am
> designing with. And
> then the classic design question arises: Serial or parallel
> load? 13*8 bits =
> 104 bits to clock in serially. Parallel is quicker, but
> takes 8 data lines
> plus 4 address lines plus one latch line equals 13 lines.
> That is a lot for a
> small processor. Ah, the like of an engineer.
> > > 
> > > Bottom line: Cool idea, is feasable, it's
> gonna take some work.
> > > 
> > > --TimR
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> 
> Harry Bissell & Nora Abdullah 4eva