# [sdiy] variable width pulse wave for JEFT sample and hold

David G. Dixon dixon at interchange.ubc.ca
Wed Jan 7 23:27:57 CET 2009

```...by the way, one doesn't actually learn this stuff until one tries to
design something.  This has been a very instructive little exercise, trying
to convert a square to a useful ramp (don't spoil it by telling me how!).

David G. Dixon
Professor
Department of Materials Engineering
University of British Columbia
Vancouver, B.C.  V6T 1Z4

Tel 1-604-822-3679
Fax 1-604-822-3619

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-----Original Message-----
From: Ian Fritz [mailto:ijfritz at comcast.net]
Sent: Wednesday, January 07, 2009 12:33 PM
To: David G. Dixon; 'Dan Snazelle'; lanterma at ece.gatech.edu; 'sdiy'
Subject: RE: [sdiy] variable width pulse wave for JEFT sample and hold

At 11:19 AM 1/7/2009, David G. Dixon wrote:
>I've been working on a circuit (based on a question of yours, actually) and
>in this circuit, I have a very simple little sample-and-hold which is
>sampling a voltage staircase from a DAC at a moment in time determined by
>the firing of an n-channel JFET.......

Sounds workable (provided the pinchoff voltage is <5V), but unnecessarily
complicated.  Why not use the conventional approach?

Sent your pulses into the (+) In of an opamp comparator.  Bias the (-) In
at ~+.5V (diode + resistor).  The output swings from V-  to  V+ when your
pulses cross .5V.

Comparator output through series diode to FET G to hold the FET normally
off.  1M resistor from FET S to G to self bias FET on during pulse.

Ian

```