[sdiy] variable width pulse wave for JEFT sample and hold

[Ian Fritz]

At 11:19 AM 1/7/2009, David G. Dixon wrote:
>I've been working on a circuit (based on a question of yours, actually) and
>in this circuit, I have a very simple little sample-and-hold which is
>sampling a voltage staircase from a DAC at a moment in time determined by
>the firing of an n-channel JFET.......

Sounds workable (provided the pinchoff voltage is <5V), but unnecessarily 
complicated.  Why not use the conventional approach?

Sent your pulses into the (+) In of an opamp comparator.  Bias the (-) In 
at ~+.5V (diode + resistor).  The output swings from V-  to  V+ when your 
pulses cross .5V.

Comparator output through series diode to FET G to hold the FET normally 
off.  1M resistor from FET S to G to self bias FET on during pulse.

   Ian