[sdiy] variable width pulse wave for JEFT sample and hold

Wed Jan 7 19:19:44 CET 2009

Dan,

Happy to help.  I'm trying to learn this stuff too, but the professor in me
keeps popping out (sometimes with the wrong answer, in classic professor
fashion!).

I've been working on a circuit (based on a question of yours, actually) and
in this circuit, I have a very simple little sample-and-hold which is
sampling a voltage staircase from a DAC at a moment in time determined by
the firing of an n-channel JFET.  To fire the JFET, I've created a square
wave with an op-amp relaxation oscillator (one TL07x, three resistors and a
cap), and sent the result through an RC differentiator (literally just a
capacitor and a resistor) to get positive and negative pulses.  Then I've
taken these pulses (which rise and fall from ground), and an inverted
version of the voltage staircase from the DAC, and summed them in an op-amp
inverting adder with a -5 V offset (a 2:1 voltage divider at the positive
input between -15 V and ground).  This gives me a replica of the voltage
staircase I am sampling, only 5 V lower, and with a positive pulse in the
middle of the period from my relaxation oscillator square wave.  It has
negative pulses too, but these are of no concern.

The voltage staircase is fed to the Source of the JFET, and the -5 V shifted
replica with the triggering pulses is fed to the Gate of the JFET.  In this
way, the gate will always be exactly 5 V lower than the source (and
therefore, the JFET will always be fully off) until the pulse (roughly a
10-us spike) comes through and activates the JFET to enable the S&H
capacitor to sample the voltage at that instant from the staircase.  This is
what I call "biasing" the gate of the JFET.  JFETs are voltage-controlled
devices (as opposed to BJTs which are current-controlled devices) so JFETs
require voltage bias (whereas BJTs require current bias).

So far, I've only simulated this setup in Multisim, but it should work very
well, and is a whole lot cheaper than a bunch of CMOS parts (about 50 cents
for all the parts required -- as I've said, I love cheap circuits!).

I hope this makes the use of JFET switches a little bit clearer.  Of course,
some of the grey eminences on this list will probably have lots of
(constructive) criticism to offer concerning my technique...

David G. Dixon
Professor
Department of Materials Engineering
University of British Columbia
309-6350 Stores Road
Vancouver, B.C.  V6T 1Z4
Canada

Tel 1-604-822-3679
Fax 1-604-822-3619

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-----Original Message-----
From: Dan Snazelle [mailto:subjectivity at hotmail.com] 
Sent: Wednesday, January 07, 2009 12:59 AM
To: dixon at interchange.ubc.ca; lanterma at ece.gatech.edu; sdiy
Subject: RE: [sdiy] variable width pulse wave for JEFT sample and hold

thanks david

your help has been greatly appreciated today!

i got out my copy of Hor and HIll and wow...great chapter!!!

i now have a list of things to try.

thanks to all who helped!

--------------------------------------------
check out various dan music at:

http://www.myspace.com/lossnyc

http://www.soundclick.com/lossnyc.htm

http://www.indie911.com/dan-snazelle
(or for techno) http://www.myspace.com/snazelle

----------------------------------------
> Date: Wed, 7 Jan 2009 00:33:21 -0800
> From: dixon at interchange.ubc.ca
> Subject: RE: [sdiy] variable width pulse wave for JEFT sample and hold
> To: lanterma at ece.gatech.edu; synth-diy at dropmix.xs4all.nl
> CC: subjectivity at hotmail.com
>
> A JFET has a gate (G), a source (S) and a drain (D). The gate is like the
> base on a BJT, the source is like the emitter, and the drain is like the
> collector. Just like the flow through a BJT is controlled by the voltage
> difference between the base and the emitter (V_BE), so the JFET is
> controlled by the voltage difference between the gate and the source
(V_GS).
>
> However, JFETs are OFF when V_GS is negative (gate voltage less than
source
> voltage) by about 4 V. Hence, if the source is at ground (common source),
> the gate must be held negative to prevent flow through the JFET. If the
> source is at ground, then putting the gate at ground will turn the JFET
> fully on. However, it's the difference which drives the device. Hence, if
> the source is at 5 V, the JFET will be fully off when the gate is below
> about 1.5 V and fully on when the gate is at about 5 V.
>
> Clear as mud? Look at Figure 3.8 in H&H. Using JFETs as switches can be a
> little bit tricky if the source voltage is moving around, but it's not
that
> different from BJTs, except that virtually no gate current flows (unlike
the
> small base current in a BJT).
>
>
> David G. Dixon
> Professor
> Department of Materials Engineering
> University of British Columbia
> 309-6350 Stores Road
> Vancouver, B.C. V6T 1Z4
> Canada
>
> Tel 1-604-822-3679
> Fax 1-604-822-3619
>
> "PERFECTA FINGAMUS SERVIAT NATURA"
>
> The information in this email and in any attachments is confidential and
> intended solely for the attention and use of the named addressee(s). It
> must not be disclosed to any person without the writer's authority. If you
> are not the intended recipient, or a person responsible for delivering it
to
> the intended recipient, you are not authorized to and must not disclose,
> copy, distribute, or retain this message or any part of it.
>
> -----Original Message-----
> From: synth-diy-bounces at dropmix.xs4all.nl
> [mailto:synth-diy-bounces at dropmix.xs4all.nl] On Behalf Of Aaron Lanterman
> Sent: Tuesday, January 06, 2009 11:58 PM
> To: SDIY DIY
> Subject: Re: [sdiy] variable width pulse wave for JEFT sample and hold
>
> On Jan 7, 2009, at 2:54 AM, Dan Snazelle wrote:
>
>> what does positive with respect to the source mean?
>
> Uhm, I haven't been following that thread, but I suspect that it means
> the voltage on whatever they were referring to is greater than the
> voltage on the source...
>
> - Aaron
>
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