[sdiy] New TOG board: $0.02 needed

[Tim Ressel]

--- On Tue, 1/6/09, David Moylan <dave at westphila.net> wrote:

> Any chance of varying the duty cycle dynamically?

Hmmm. There are 2 problems. The first is getting the data into the part. Are we talking about varying all 13 note at the same time and by the same amount? I assume we are. The second problem is more nasty. A variable PWM would have to be a number that varies from 1 to the max count of the counter minus 1. The problem is each note has a different max count. So if we try to load a single PWM number and use it on all the note counters, we get different PWMs for each note. The lowest note will get a full range while the highest note will only make it to 50%. I deem this too much to be useful.

So we need to load a different value for each note. This is possible. I'm note sure it will fit into the current CPLD family I am designing with. And then the classic design question arises: Serial or parallel load? 13*8 bits = 104 bits to clock in serially. Parallel is quicker, but takes 8 data lines plus 4 address lines plus one latch line equals 13 lines. That is a lot for a small processor. Ah, the like of an engineer.

Bottom line: Cool idea, is feasable, it's gonna take some work.

--TimR