[sdiy] variable width pulse wave for JEFT sample and hold

Wed Jan 7 12:35:12 CET 2009

Dan,

If you're trying for such a bit crushing effect (actually sample-rate 
reduction) then perhaps you should look instead at using a switch IC 
instead of the JFET - you will find the 'interface' circuitry to be much 
easier.

For unipolar supply try CMOS 4016 / 4066
For Bipolar you'd want something like the DG range of switches - just a 
single SPST switch is needed.

Hope that helps?!

Tom

Dan Snazelle wrote:
> well than i am REALLY confused. all night i was pissed. i could not get anything to CLOCK the bit crusher (colin's) other than the original clock circuit he came up with which was NOT voltage controllable. (dual opamp clock)
>
> i was looking for something less parts, easier....cv controllable. 
>
> SO.....i tried synthmongers 40106 vco. which says it puts out a narrow pulse for just these types of circuits.
>
> no go
>
> so after someone saying JFETS trigger on neg voltages, i said wait a minute.
>
> i reverted to a super simple 40106 clock EXCEPT i plugged pin 14 into gnd and pin 7 into -12volts (through a 10k resistor)
>
> (keep in mind i have my clock signal going into the jfet through a 1m resistor)
>
> ok...IT WORKED
>
>
> well
>
> so tomorrow i will go back to  voltage controlling the 40106 but with everything using -v as the gnd.
>
>
> why did this work?
>
> i am very happy...this was a frustrating day!
>
> --------------------------------------------
> check out various dan music at:
>
> http://www.myspace.com/lossnyc  
>
>
> http://www.soundclick.com/lossnyc.htm
>
>
> http://www.indie911.com/dan-snazelle
> (or for techno) http://www.myspace.com/snazelle 
>
>
>
>
>   
>> Date: Tue, 6 Jan 2009 23:22:43 -0800
>> From: dixon at interchange.ubc.ca
>> Subject: RE: [sdiy] variable width pulse wave for JEFT sample and hold
>> To: subjectivity at hotmail.com; ijfritz at comcast.net; synth-diy at dropmix.xs4all.nl
>>
>> Dan,
>>
>> No, an N-channel JFET is fully on when the difference between its gate
>> voltage and its source voltage (V_GS) is about 0 V.  The JFET passes no
>> current when V_GS is less than about -3.5 volts.  Please refer to Figure 3.8
>> of Horowitz and Hill (2nd edition) for the full story.  The device is
>> triggered by a positive pulse, but from a negative bias against the source
>> voltage.
>>
>> JFETs can be fairly tricky to use because of this.
>>
>> David G. Dixon
>> Professor
>> Department of Materials Engineering
>> University of British Columbia
>> 309-6350 Stores Road
>> Vancouver, B.C.  V6T 1Z4
>> Canada
>>  
>> Tel 1-604-822-3679
>> Fax 1-604-822-3619
>>  
>> "PERFECTA FINGAMUS SERVIAT NATURA"
>>
>> The information in this email and in any attachments is confidential and
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>>
>> -----Original Message-----
>> From: Dan Snazelle [mailto:subjectivity at hotmail.com] 
>> Sent: Tuesday, January 06, 2009 6:58 PM
>> To: ijfritz at comcast.net; dixon at interchange.ubc.ca; sdiy
>> Subject: RE: [sdiy] variable width pulse wave for JEFT sample and hold
>>
>>
>> ok...so it sounds like a n channel fet gets triggered by a NEGATIVE pulse.
>>
>> i will check everyones great ideas
>>
>> thanks!!
>>
>>
>>
>>
>>
>>
>> --------------------------------------------
>> check out various dan music at:
>>
>> http://www.myspace.com/lossnyc
>>
>>
>> http://www.soundclick.com/lossnyc.htm
>>
>>
>> http://www.indie911.com/dan-snazelle
>> (or for techno) http://www.myspace.com/snazelle
>>
>>
>>
>>
>>
>>
>> ----------------------------------------
>>     
>>> Date: Tue, 6 Jan 2009 11:49:05 -0700
>>> To: dixon at interchange.ubc.ca; subjectivity at hotmail.com;
>>>       
>> synth-diy at dropmix.xs4all.nl
>>     
>>> From: ijfritz at comcast.net
>>> Subject: RE: [sdiy] variable width pulse wave for JEFT sample and hold
>>>
>>> Or use Bernie's S/H technique. Fire a 555 timer powered between 0V and
>>>       
>> -15V.
>>     
>>> At 11:19 AM 1/6/2009, David G. Dixon wrote:
>>>
>>>       
>>>> Why not just use an RC high-pass filter with a time constant of about 10
>>>>         
>> us
>>     
>>>> to generate spikes from the square (0.001 uF and 10 k will do nicely), and
>>>> then shift the pulses with a unity-gain inverting opamp with a voltage 2:1
>>>> divider off the positive input between -15V and 0V so that the output DC
>>>> rides at about -5V and the spikes go up to 0V to trigger the JFET (which,
>>>>         
>> I
>>     
>>>> presume, is npn and therefore is full off at about -3.5V and full on at
>>>> about 0V)?
>>>>         
>
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