[sdiy] variable width pulse wave for JEFT sample and hold

[David G. Dixon]

A JFET has a gate (G), a source (S) and a drain (D).  The gate is like the
base on a BJT, the source is like the emitter, and the drain is like the
collector.  Just like the flow through a BJT is controlled by the voltage
difference between the base and the emitter (V_BE), so the JFET is
controlled by the voltage difference between the gate and the source (V_GS).

However, JFETs are OFF when V_GS is negative (gate voltage less than source
voltage) by about 4 V.  Hence, if the source is at ground (common source),
the gate must be held negative to prevent flow through the JFET.  If the
source is at ground, then putting the gate at ground will turn the JFET
fully on.  However, it's the difference which drives the device.  Hence, if
the source is at 5 V, the JFET will be fully off when the gate is below
about 1.5 V and fully on when the gate is at about 5 V.

Clear as mud?  Look at Figure 3.8 in H&H.  Using JFETs as switches can be a
little bit tricky if the source voltage is moving around, but it's not that
different from BJTs, except that virtually no gate current flows (unlike the
small base current in a BJT).


David G. Dixon
Professor
Department of Materials Engineering
University of British Columbia
309-6350 Stores Road
Vancouver, B.C.  V6T 1Z4
Canada
 
Tel 1-604-822-3679
Fax 1-604-822-3619
 
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-----Original Message-----
From: synth-diy-bounces at dropmix.xs4all.nl
[mailto:synth-diy-bounces at dropmix.xs4all.nl] On Behalf Of Aaron Lanterman
Sent: Tuesday, January 06, 2009 11:58 PM
To: SDIY DIY
Subject: Re: [sdiy] variable width pulse wave for JEFT sample and hold

On Jan 7, 2009, at 2:54 AM, Dan Snazelle wrote:

> what does positive with respect to the source mean?

Uhm, I haven't been following that thread, but I suspect that it means  
the voltage on whatever they were referring to is greater than the  
voltage on the source...

- Aaron

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