[sdiy] Soft sync?

[Scott Gravenhorst]

"David G. Dixon" <dixon at interchange.ubc.ca> wrote:
>Newbie alert:
>
>I know that "hard sync" is overriding an oscillator's integrator reset with
>an external trigger.  What is "soft sync"?
>

There is more than one definition, others have given a purpose driven intentional
interface type of soft synch.  Another is a reference to unintentional and undesired
coupling of one oscillator to another.  This can be the result of trying to share
multiple opamps in a single package between two or more VCOs or poor or nonexistent
power supply bypassing.

This can also be (as with the FatMan) a design which coupled VCOs together via the power
supply lines.  In the FatMan, using bipolar 555 timers were the problem because they
have a standard design TTL totem pole output.  Totem poles were design for digital
systems for an increased logic transition speed.  The design purposefully allows BOTH
output transistors to be on simultaneously for a brief moment during transition.  This
causes a nasty current pulse such that the PS voltage drops for an instant thus coupling
the problem to anything using that voltage.  A solution in this case is to replace the
bipolar 555s with ICM7555 or equiv. CMOS timers.  These devices do not generate nearly
the current spike of the bipolar parts.

Note that other kinds of module circuits can also cause undesired synching of VCOs, not
just VCO to VCO.

-- ScottG
________________________________________________________________________
-- Scott Gravenhorst
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