[sdiy] DsPIC timer issue when used as DCO!

[Eric Brombaugh]

Do you suppose there's any significance to the fact that DSI used the MC 
(motor control) version of the dsPIC? I initially thought that they 
might have been using some of the special PWM features that are only 
available on that series, but someone else argued against it. Now I 
wonder again...

Eric

On 12/15/2009 04:59 PM, Dave Manley wrote:
> It doesn't use the output compare logic, but uses an ISR as Tom did in
> his own code. To do a hard sync, when the interrupt on TMRx occurs,
> write the value of TMRy to 0 (or any other value you want).
>
> -Dave
>
> karl dalen wrote:
>> Since it seams that 32 bit timers cant use the comparator module perhaps
>> DSI just took the brute force route and OCx output from one 16 bit timer
>> to the TxCK input of next 16bit timer? The effect would be the same and
>> compare would be available for toggling. But how did he then implement
>> the hard sync?
>>
>> Reg
>> KD
>>
>>
>>>>> Sorry if this is a dumb question (I'm new to the
>>> dsPIC range) ... but from what I can see the output compare
>>> logic only works on 16-bit timers, not on 32-bit
>>> timers. So if, as we suspect, two 16-bit timers are
>>> running in tandem to make a 32-bit timer, how would the
>>> output compare work then?
>>>> Not so dumb. I was wondering the same thing.
>>> Good point - I didn't look closely enough at the output
>>> compare circuit to notice they were 16-bit only. If
>>> you were only trying to generate the standard note
>>> frequencies then a 16-bit timer is enough, but that won't
>>> handle smooth modulation/portamento/etc.
>
>
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