[sdiy] DsPIC timer issue when used as DCO!

[karl dalen]

--- Den fre 2009-12-11 skrev Tom Wiltshire <tom at electricdruid.net>:
 
> I think you're thinking about doing it a different way to
> how I was thinking about doing it!

yes why not, every darn timer are different from every darn manufacturer!
Dont mess with the MSP430 timers your brain will go ape!

> Output compare (OC) is a separate feature, and I wouldn't
> have thought you needed it for generating DCO reset pulses
> (I didn't need it).
> 
> Looking through the chapter on it, I can see that it does
> look rather appealing for the job in hand, though - assuming
> it can be made to work with 32-bit counters.
> 
> If that's how DSI did it, then I think they missed this
> bit! -
> "The user application must disable the associated timer
> when writing to the output compare control registers to
> avoid malfunctions."

Yes but this does not explain the slow rising ramp as we see in the picture!
 
> > Whats the difference between PRx and TMRx in
> comparator toggle mode?
> 
> TMRx is the actual count, the number of master clock pulses
> that have arrived at the counter. PRx is the "Match" value.
> When TMRx matches PRx, the counter is reset (TMRx = 0), and
> an interrupt is generated. This *does* work with
> concatenated 32-bit counters.
> 
> The way I did it was to use the interrupt routine to then
> set a pin high to reset the ramp generator. Interrupt
> latency isn't much of an issue. It takes 5 cycles, which at
> the max clock of 40MHz is 125nS. Most analogue ramp resets
> are measured in uS, so you've got time to get your reset
> pulse out *and* get the kettle on before a full uSec has
> elapsed.
> 
> Dave, if you're reading this, feel free to send me a
> Prophet and some code, and I'll do my best to fix it for
> you!

Hehe, god try Tom!

But i think we have overseen the whole hoopla! There is no timer error! :)

I did a rethink over the whole thing, lets look at the picture again and what do we actually see?

At the very left we have a one cykle of low triangle, the timer register
and the shape voltage are consistent with each other, now the user
suddenly plays a high note, what hapends? the Mcu loads timer register with a value and here Tom i think you are right, the load causes a rollower, reset and starts to begin a new count! becuase thats what
we see in the picture, an emideate sunth of the charg cap to low level
somewhat into the rising old triangle. (start of saw are always from lowest level, no moog vco discharge from high no).

But the problem here regarding to the picture are no the reload of the timer, its that the ISR has loaded a wrong number into the timer!
And not only that it also has demuxed out the wrong but for the frequency correct shape voltage, namely both are now at very low frequency and voltage..

Look at the slope of the wave , its slowely rising, if the timer had been loaded with the correct number but still with the wrong Shape voltage,
(a high note triangle as we see on the far right)this slowely rising
ramp would instead have been a low amplitude fast saw!
This becuse the PA397 current mirror are a rising ramp
whos shorted to AG by the NPN transistor!.

So i figure, there is no Timer problem, it's an ISR timer and CV Shape
update bug! :)

So what do you think about this argument? Big wet donkey balls? :)


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